Patents by Inventor Shih-Cheng Chen

Shih-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11093080
    Abstract: An electronic device and a fingerprint sensing control method thereof are provided. A sensing region of a display panel is divided into a plurality of fingerprint zones. The electronic device determines at least one target fingerprint zone from the fingerprint zones according to a touched area. The electronic device scans the at least one target fingerprint zone for performing fingerprint sensing. The electronic device performs an accelerated reading operation. The accelerated reading operation includes: reading at least one sensing signal from the at least one target fingerprint zone; and skipping reading at least one of the fingerprint zones other than the at least one target fingerprint zone among the fingerprint zones.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shih-Cheng Chen, Cho-Hsuan Jhang, Chih-Peng Hsia, Shiang-Fei Wang, Su-Wei Lien
  • Patent number: 11087988
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. A top surface of the dielectric fin is close to the epitaxial structure. The semiconductor device structure includes a silicide layer wrapping around the epitaxial structure and partially between the dielectric fin and the epitaxial structure. The silicide layer covers a lower surface of the epitaxial structure, and the lower surface is lower than the top surface of the dielectric fin.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Jung-Hung Chang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20210226020
    Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Pei-Hsun WANG, Chih-Hao WANG
  • Patent number: 11049774
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20210193842
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20210125927
    Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 29, 2021
    Inventors: Shih-Cheng Chen, Li-Hsuan Ho, Tsuo-Wen Lu, Shih-Hao Liang, Tsung-Hsun Wu, Po-Jen Chuang, Chi-Mao Hsu
  • Publication number: 20210126113
    Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.
    Type: Application
    Filed: May 11, 2020
    Publication date: April 29, 2021
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Lo-Heng Chang, Jung-Hung Chang, Kuo-Cheng Chiang
  • Publication number: 20210074548
    Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the epitaxial S/D feature, the silicide layer is disposed on sidewalls of the epitaxial S/D feature, a dielectric layer disposed over sidewalls of the silicide layer, and an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Patent number: 10944009
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate; an isolation structure at least partially surrounding the fin; an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein an extended portion of the epitaxial S/D feature extends over the isolation structure; and a silicide layer disposed on the epitaxial S/D feature, the silicide layer continuously surrounding the extended portion of the epitaxial S/D feature over the isolation structure.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20210066294
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 4, 2021
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20210020524
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20200381257
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. A top surface of the dielectric fin is close to the epitaxial structure. The semiconductor device structure includes a silicide layer wrapping around the epitaxial structure and partially between the dielectric fin and the epitaxial structure. The silicide layer covers a lower surface of the epitaxial structure, and the lower surface is lower than the top surface of the dielectric fin.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Jung-Hung CHANG, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20200381545
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Application
    Filed: December 5, 2019
    Publication date: December 3, 2020
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Patent number: 10847373
    Abstract: A method includes forming a first dielectric layer over a semiconductor fin protruding from a substrate, forming a second dielectric layer over the first dielectric layer, then removing a portion of the semiconductor fin to form a first recess defined by portions of the first dielectric layer, followed by removing that portions of the first dielectric layer that define the first recess. Thereafter, the method proceeds to forming an epitaxial source/drain (S/D) feature in the first recess, removing the second dielectric layer to form a second recess that is disposed between the epitaxial S/D feature and remaining portions of the first dielectric layer, and subsequently forming a silicide layer over the epitaxial S/D feature, such that the silicide layer wraps around the epitaxial S/D feature.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
  • Publication number: 20200275001
    Abstract: A display apparatus and an fingerprint sensing method thereof are provided. A display panel of the display apparatus has a pixel circuit array, an in-display touch sensor array, and an in-display fingerprint sensor array. A driving circuit drives the in-display fingerprint sensor array to read a fingerprint image. A current display frame period is divided into a plurality of unit periods, each of the unit periods includes at least one fingerprint sensing period and one or both of a display driving period and a touch sensing period. The driving circuit resets a current fingerprint sensor in the in-display fingerprint sensor array during a first fingerprint sensing period among these fingerprint sensing periods of the first display frame period. The driving circuit reads a sensing result of the current fingerprint sensor during a second fingerprint sensing period succeeding to the first fingerprint sensing period.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 27, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Cho-Hsuan Jhang, Chao-Yu Meng, Shih-Cheng Chen, Chih-Peng Hsia
  • Patent number: 10748775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a first dielectric layer over the base portion and a first sidewall of the fin portion. The method includes forming a first spacer layer over the first dielectric layer. The method includes forming a first dielectric fin over the first spacer layer. The method includes forming an epitaxial structure over the fin portion, wherein a void is surrounded by the epitaxial structure, the first dielectric layer, and the first spacer layer. The method includes removing the first spacer layer between the epitaxial structure and the first dielectric fin. The method includes forming a silicide layer over the epitaxial structure, wherein a first lower portion of the silicide layer covers a lower surface of the epitaxial structure and is in the void.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Jung-Hung Chang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20200210668
    Abstract: An electronic device and a fingerprint sensing control method thereof are provided. The electronic device includes a touch control circuit and a fingerprint sensing control circuit. The touch control circuit is coupled to the display panel. The touch control circuit performs touch detection on the display panel to obtain a finger press area corresponding to the finger on the display panel. The fingerprint sensing control circuit is coupled to the touch control circuit to obtain a finger press area. The fingerprint sensing control circuit is coupled to the display panel to perform a fingerprint sensing control on a display panel. The fingerprint sensing control circuit scans the finger press area on the display panel in a first direction during a first period and scans the finger press area in a second direction different from the first direction during a second period after the first period.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 2, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Cho-Hsuan Jhang, Shih-Cheng Chen, Su-Wei Lien, Chih-Peng Hsia, Shiang-Fei Wang
  • Publication number: 20200210065
    Abstract: An electronic device and a fingerprint sensing control method thereof are provided. A sensing region of a display panel is divided into a plurality of fingerprint zones. The electronic device determines at least one target fingerprint zone from the fingerprint zones according to a touched area. The electronic device scans the at least one target fingerprint zone for performing fingerprint sensing. The electronic device performs an accelerated reading operation. The accelerated reading operation includes: reading at least one sensing signal from the at least one target fingerprint zone; and skipping reading at least one of the fingerprint zones other than the at least one target fingerprint zone among the fingerprint zones.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Shih-Cheng Chen, Cho-Hsuan Jhang, Chih-Peng Hsia, Shiang-Fei Wang, Su-Wei Lien
  • Publication number: 20200135932
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate; an isolation structure at least partially surrounding the fin; an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein an extended portion of the epitaxial S/D feature extends over the isolation structure; and a silicide layer disposed on the epitaxial S/D feature, the silicide layer continuously surrounding the extended portion of the epitaxial S/D feature over the isolation structure.
    Type: Application
    Filed: September 25, 2019
    Publication date: April 30, 2020
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20200126798
    Abstract: A method includes forming a first dielectric layer over a semiconductor fin protruding from a substrate, forming a second dielectric layer over the first dielectric layer, then removing a portion of the semiconductor fin to form a first recess defined by portions of the first dielectric layer, followed by removing that portions of the first dielectric layer that define the first recess. Thereafter, the method proceeds to forming an epitaxial source/drain (S/D) feature in the first recess, removing the second dielectric layer to form a second recess that is disposed between the epitaxial S/D feature and remaining portions of the first dielectric layer, and subsequently forming a silicide layer over the epitaxial S/D feature, such that the silicide layer wraps around the epitaxial S/D feature.
    Type: Application
    Filed: June 18, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang