Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.

Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electro-static discharge protection due to the sacrificial electrodes are broken.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electro-static discharge protection due to the sacrificial electrodes are broken.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electrostatic discharge protection due to the sacrificial electrodes are broken.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electrostatic discharge protection due to the sacrificial electrodes are broken.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electro-static discharge protection due to the sacrificial electrodes are broken.

Abstract: Sacrificial electrodes with fractal-shaped are formed on a SAW (surface acoustic wave) device. The sacrificial electrodes discharge electro-static charge in the SAW device for protecting the IDT (inter-digital transducer) from electrostatic break. Moreover, the sacrificial electrodes can control the path and the discharging degree of the electro-static discharge to avoid losing the electrostatic discharge protection due to the sacrificial electrodes are broken.