Abstract: A memory device includes a substrate, a 2-D material channel layer, a 2-D material charge storage layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The 2-D material channel layer is over the substrate. The 2-D material charge storage layer is over the 2-D material channel layer. The 2-D charge storage layer and the 2-D material channel layer include the same chalcogen atoms. The source/drain contacts are over the 2-D material channel layer. The gate dielectric layer covers the source/drain contacts and the 2-D material charge storage layer. The gate electrode is over the gate dielectric layer.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: A wafer lithographic shielding mask for fabricating a multi-project wafer (MPW) and a wafer fabrication method using the same are disclosed. The mask including a light shielding layer and at least one transparent region is used to select the layout patterns of designated chips on an MPW reticle to be exposed onto the photoresist layer on the surface of the wafer. The lithography method of fabricating MPW mainly involves disposing a wafer lithographic shielding mask for selecting the exposure regions on the MPW reticle on the light transmission path from a lithographic light source to a wafer, e.g., between the MPW reticle and the lithographic light source or between the MPW reticle and the wafer, so as to prevent some undesired chips from being fabricated on the wafer using the MPW reticle, thereby decreasing the wafer production cost.

Abstract: A wafer lithographic shielding mask for fabricating a multi-project wafer (MPW) and a wafer fabrication method using the same are disclosed. The mask including a light shielding layer and at least one transparent region is used to select the layout patterns of designated chips on an MPW reticle to be exposed onto the photoresist layer on the surface of the wafer. The lithography method of fabricating MPW mainly involves disposing a wafer lithographic shielding mask for selecting the exposure regions on the MPW reticle on the light transmission path from a lithographic light source to a wafer, e.g., between the MPW reticle and the lithographic light source or between the MPW reticle and the wafer, so as to prevent some undesired chips from being fabricated on the wafer using the MPW reticle, thereby decreasing the wafer production cost.

Abstract: A multi-functional timer comprises a CPU connected respectively with a setting unit, display unit, output control circuit and oscillating circuit. The setting unit has several switches; the switches are connected to several buttons on a panel. The display unit has a display zone, setting date display zone and date/time display zone. Digits 1 to 7, which represent Monday to Sunday, can be shown at the setting date display zone. The display zone is also combined onto the panel. The timer according to the present can be simpler on the setting operation of a work time and can be used to set different work time sections as well as to set every kind of action interval in a work time section.