Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: An anti-PD-L1 antibody, or an antigen-binding fragment thereof, comprising: a heavy chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 2-4, 6-8, 10-12, 14-16, or 18-20; and/or a light chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 22-24, 26-28, 30-32, 34-36, or 38-40, wherein the antibody is a chimeric, humanized, composite, or human antibody.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, forming a contact opening on the S/D region, forming a semiconductor nitride layer on a sidewall of the contact opening, performing a densification process on the semiconductor nitride layer to form a densified semiconductor nitride layer, forming a silicide layer on an exposed surface of the S/D region in the contact opening, forming a contact plug in the contact opening, and forming a via structure in the contact plug.

Abstract: This invention discloses an injection molding machine and a heat-insulating structure of a barrel thereof. The heat-insulating structure covers the barrel of the injection molding machine. The heat-insulating structure includes a plurality of heat-insulating units and a plurality of heat-resistant interlinings. The heat-insulating units are disposed on an outer surface of the barrel in turn along an axial direction of the barrel. The heat-resistant interlinings are located between the heat-insulating units and connect the heat-insulating units, respectively. Each heat-insulating unit includes a heat-resistant layer, a heat-insulating material layer, and an insulating layer in turn. The heat-resistant layer covers the outer surface of the barrel of the injection molding machine.

Abstract: This invention discloses an injection molding machine and a heat-insulating structure of a barrel thereof. The heat-insulating structure covers the barrel of the injection molding machine. The heat-insulating structure includes a plurality of heat-insulating units and a plurality of heat-resistant interlinings. The heat-insulating units are disposed on an outer surface of the barrel in turn along an axial direction of the barrel. The heat-resistant interlinings are located between the heat-insulating units and connect the heat-insulating units, respectively. Each heat-insulating unit includes a heat-resistant layer, a heat-insulating material layer, and an insulating layer in turn. The heat-resistant layer covers the outer surface of the barrel of the injection molding machine.

Abstract: This present invention provides methods for isolating interconnects characterized by first isolating the top and bottom interconnects with an IMD consisting of a traditional low-k dielectric material, then dissolving the low-k material with a suitable solvent and using air or a noble gas instead of the traditional low-k dielectric material to isolate the interconnects.

Abstract: The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.

Abstract: A method for fabricating a DRAM capacitor is described. First, a semiconductor substrate having a capacitor contact is provided. Next, a first polysilicon layer is formed. Then, an oxide layer and a silicon oxy-nitride layer are sequentially formed over the first polysilicon layer. Next, the silicon oxy-nitride layer, the oxide layer, and the first polysilicon layer are selectively etched to leave a rectangular stack layer. Afterwards, the oxide layer and the first polysilicon layer of the rectangular stack layer are etched from the sidewall direction to leave a double T-shaped stack layer. Then, second polysilicon layer is formed on the upper surface and the sidewall of the double T-shaped stack layer. Next, the second polysilicon layer is selectively removed. The remaining second and first polysilicon layer are used as the bottom electrode. Afterwards, a dielectric layer and an upper electrode are formed on the bottom electrode.