Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.

Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.

Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.

Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.

Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.