Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Abstract: An embodiment of the invention provides a method of processing a radio frequency (RF) signal. According to the embodiment, the RF signal is first synthesized with a synthesis signal to generate a synthesized signal. Then, the synthesized signal is filtered with a filtering bandwidth to generate a filtered signal. Next, the filtered signal is converted into digital data. Then, the digital data is processed to analyze a plurality of carriers within the filtering bandwidth as presented in the RF signal.

Abstract: A method for measuring mismatches in a digitally-controlled oscillator (DCO) includes: in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, and controlling a second capacitor array of the DCO in a closed loop to make a frequency of the DCO locked to a target value; in a second settling phase, controlling the first capacitor array to consistently have a second capacitive value different from the first capacitive value, and controlling the second capacitor array in the closed loop to make the frequency of the DCO locked to the target value; and deriving an estimation from a difference value between a first characteristic value and a second characteristic value, wherein the first and second characteristic values are derived from the digital control word; and estimating the mismatches according to at least the estimation value.

Abstract: The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Abstract: The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Abstract: The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Abstract: A MIMO OFDM system for TICM includes a tone-level interleaver at the transmitter using a block of NT symbols as its basic unit. This results in different decoding architectures at the receiver. The main advantage of TICM is to merge soft-bit demapping into the Viterbi algorithm. Taking advantage of the trellis structure inherent in the Viterbi algorithm, TICM can have lower computational complexity and potentially better performance than BICM with the LSD detector and the vector demapper. Although the tone-level interleaving may not have spatial diversity gain, the performance is not affected in 802.11n environments.

Abstract: The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Abstract: Wireless transmitted system and apparatus and method for encoding a plurality of information bits to a plurality of transmitted signals thereof, and wireless received system and apparatus and method for decoding a received signal to a plurality of information bits thereof are provided. The wireless transmitted system encodes a plurality of information bits to a plurality of transmitted signals by two logic operation modules, an interleaving module, and a combination module. The wireless received system decodes a received signal to a plurality of information bits by a division module, two probability generation modules, two status calculation modules, a signal generation module and a combination module.

Abstract: A MIMO OFDM system for TICM is provided. The tone-level interleaver at the transmitter uses a block of NT symbols as its basic unit. This results in different decoding architectures at the receiver. The main advantage of TICM is to merge soft-bit demapping into the Viterbi algorithm. Taking the advantage of the trellis structure inherent in the Viterbi algorithm, TICM can have lower computational complexity and potentially better performance than BICM with the LSD detector and the vector demapper. Although the tone-level interleaving may not have spatial diversity gain, the performance is not affected in 802.11n environments.