Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

Abstract: A furniture assembly includes a first object, a second object, a self-closing device, an aiding member, an interlock mechanism and an actuating part. The second object is displaceable relative to the first object. The self-closing device is arranged on the first object and includes a base, a working member and a resilient member. The working member and the aiding member are movable relative to the base. The interlock mechanism is arranged on the first object. The actuating part is arranged on the second object. When the second object is located at the extended position and the working member returns to an initial position from an engaging position in response to a self-closing resilient force provided by the resilient member, the aiding member is located at a predetermined position to retain at least one locking member of the interlock mechanism at a locking position.

Abstract: A mask includes a reflective layer, an absorption layer, a buffer layer and an absorption part. The absorption layer is disposed over the reflective layer. The buffer layer is disposed between the reflective layer and the absorption layer. The absorption part is disposed in the reflective layer, the buffer layer and the absorption layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

Abstract: Disclosed is an anti-deposition object with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a substance in an environment, the fluorine coating layer has a water droplet contact angle with the substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.

Abstract: Disclosed is an anti-deposition object for use in a vacuum environment with a main structure and a fluorine coating layer, the fluorine coating layer covers at least one surface of the main structure, the anti-deposition object contacts with a manufacturing process substance used or discharged during a manufacturing process performed by a manufacturing process equipment in the vacuum environment, the fluorine coating layer has a water droplet contact angle with the manufacturing process substance higher than that of the surface of the main structure, the fluorine coating layer has a hardness similar to or higher than that of the surface of the main structure, and the fluorine coating layer has a roughness lower than that of the surface of the main structure.

Abstract: A method of fabricating a semiconductor device includes forming, over a substrate, alternating layers of a first semiconductor layer formed of a first semiconductor material and a second semiconductor layer formed of a second semiconductor material, the first semiconductor layers including a first, a second, and a third sub-layers; patterning the alternating layers of the first and the second semiconductor layers to form stacks of the alternating layers; and exposing, under etch conditions, lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.

Abstract: An adjustment device of a slide rail mechanism includes a base, a driving member and an adjusting member. The adjusting member is arranged on the base. The adjusting member is configured to be adjusted for moving the driving member. The adjustment device can be used with a working member to form an interlock mechanism. The interlock mechanism only allows a rail of one of the slide rail assemblies of the slide rail mechanism to be opened.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A manufacturing method of the circuit board includes the following steps. A metal layer, a first substrate, a second substrate, and a third substrate are laminated. Multiple blind holes and a through hole are formed. A conductive material layer is formed, which covers the metal layer, the conductive layer of the third substrate, and an inner wall of the through hole, and fills the blind holes to define multiple conductive holes. The conductive material layer, the metal layer, and the conductive layer are patterned to form a first external circuit layer located on the first substrate and electrically connected to the conductive pillars, and a second external circuit layer located on the insulating layer and electrically connected to the conductive holes, and define a conductive through hole structure connecting the first external circuit layer and the second external circuit layer and located in the through hole.

Abstract: A mask includes a reflective layer, an absorption layer and an absorption part. The absorption layer is disposed over the reflective multilayer. The absorption part is disposed in the reflective layer and the absorption layer, wherein an entire top surface of the absorption part is substantially flush with a top surface of the absorption layer.

Abstract: A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path.

Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.

Abstract: A slide rail mechanism is configured to a cabinet. The cabinet includes a wall with a first side and a second side opposite to the first side. The slide rail mechanism includes a first slide rail assembly, a second slide rail assembly and a working member. When a second rail of the first slide rail assembly is opened with respect to a first rail, the second rail is able to drive the working member for preventing a fourth rail of the second slide rail assembly to be opened with respect to a third rail.

Abstract: A slide rail mechanism is configured to a cabinet. The slide rail mechanism includes a first rail assembly, a second rail assembly and a working member. The first and second assemblies are arranged on the cabinet. The working member is shiftable with respect to the cabinet. When a second rail of the first rail assembly is opened with respect to a first rail, the working member is moved in a transverse direction for preventing a fourth rail of the second rail assembly to be opened from a retracted position with respect to a third rail.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.