Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Abstract: A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

Abstract: An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.

Abstract: A color display device includes a plurality of pixel display elements and a driving circuit. Each of the pixel display elements includes a plurality of sub-pixel display elements. Each of the sub-pixel display elements includes first and second supports, first and second electrodes attached to inner faces of the first and second supports, respectively, a solution disposed between the first and second electrodes, and particles dispersed in the solution. The particles of the sub-pixel display elements of a same one of the pixel display elements are electrically polarizable by voltage signals supplied by the driving circuit, the voltage signals having the same predetermined driving frequency.

Abstract: A color display device includes a plurality of pixel display elements and a driving circuit. Each of the pixel display elements includes a plurality of sub-pixel display elements. Each of the sub-pixel display elements includes first and second supports, first and second electrodes attached to inner faces of the first and second supports, respectively, a solution disposed between the first and second electrodes, and particles dispersed in the solution. The particles of the sub-pixel display elements of a same one of the pixel display elements are electrically polarizable by voltage signals supplied by the driving circuit, the voltage signals having the same predetermined driving frequency.

Abstract: A vehicle brake warning device for use in a vehicle with a brake pedal includes a detector for producing different electrical signals in response to the magnitude of the inertia force experienced during braking, a control circuitry receiving signals from the detector and having a varying frequency output depending upon the received signal, and a warning device activated by the varying frequency output of the control circuitry. Whenever a pressing force is exerted on the brake pedal to reduce the speed of the vehicle, the detector experiences an inertia force whose magnitude depends upon the speed of the vehicle. The detector sends out an appropriate signal dependent upon the magnitude of the inertia force to the control circuitry. The control circuitry activates the warning device to send out a warning signal which varies depending upon the magnitude of the inertia force.