Patents by Inventor Shih-Chiang Huang

Shih-Chiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for fabricating the same
    Patent number: 12237394
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Method for growing Ge expitaxial layer on patterned structure with cyclic annealing
    Patent number: 7851378
    Abstract: A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: December 14, 2010
    Assignee: National Applied Research Laboratories
    Inventors: Ming-Hsin Cheng, Shih-Chiang Huang, Tsung-Chieh Cheng, Guang-Li Luo, Chinq-Long Hsu
  • Method for growing Ge expitaxial layer on patterned structure with cyclic annealing
    Publication number: 20100216298
    Abstract: A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device.
    Type: Application
    Filed: September 11, 2007
    Publication date: August 26, 2010
    Applicant: National Applied Research Laboratories
    Inventors: Ming-Hsin Cheng, Shih-Chiang Huang, Tsung-Chieh Cheng, Guang-Li Luo, Chinq-Long Hsu
  • Manufacturing method for nano scale Ge metal structure
    Publication number: 20090221144
    Abstract: Manufacturing methods for nano scale Ge include: Form dielectric layer on the substrate surface, then etch the dielectric layer to form openings of three different dimensions, then use chemical vapor deposition process to deposit Ge metal layer to cover the substrate, dielectric layer and the openings; then on the opening of three different dimensions, nano-dot, nano-disk and nano-ring are formed.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 3, 2009
    Inventors: Ming-Hsin Cheng, Shih-Chiang Huang, Wei-Xin Ni, Guang-Li Luo