Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.

Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.

Abstract: A controlling method is provided for preventing a solid state drive from being operated at a high temperature. The solid state drive includes a controlling circuit, a temperature detecting circuit and a plurality of dies. The dies are divided into n groups and accessed by the controlling circuit through n IO buses. The controlling circuit is in communication with the temperature detecting circuit for detecting a temperature of the solid state drive. The controlling method includes the following steps. Firstly, a judging step is performed to judge whether the temperature of the solid state drive is higher than a predetermined temperature. If the temperature of the solid state drive is higher than the predetermined temperature, the frequencies of n clock signals in the n IO buses are decreased.

Abstract: A controlling method is provided for preventing a solid state drive from being operated at a high temperature. The solid state drive includes a controlling circuit, a temperature detecting circuit and a plurality of dies. The dies are divided into n groups and accessed by the controlling circuit through n IO buses. The controlling circuit is in communication with the temperature detecting circuit for detecting a temperature of the solid state drive. The controlling method includes the following steps. Firstly, a judging step is performed to judge whether the temperature of the solid state drive is higher than a predetermined temperature. If the temperature of the solid state drive is higher than the predetermined temperature, the frequencies of n clock signals in the n IO buses are decreased.