Patents by Inventor Shih-Chieh Chang

Shih-Chieh Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240241185
    Abstract: This disclosure provides an estimation method applied to a state of health of a battery, which executes a recharging to a battery when a battery voltage is lower than a threshold voltage. During the recharging, a battery state of health estimation procedure is performed from a first depth of discharge detection point to a second depth of discharge detection point. During the battery state of health estimation procedure, a voltage difference between a current battery voltage and an initial open-circuit voltage is accumulated over time from the first depth of discharge detection point to the second depth of discharge detection point to obtain an accumulation of current sampled voltage difference. An accumulation of estimated DC internal resistances can be equivalently obtained by the accumulation of current sampled voltage difference. Afterwards, the state of health of the battery can be determined based on the accumulation of estimated DC internal resistance.
    Type: Application
    Filed: July 11, 2023
    Publication date: July 18, 2024
    Inventors: Wen-Fan Chang, Chun-Chieh Li, Shih-Fa Hung, Jian-Min Chen
  • Publication number: 20240234548
    Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a fin structure extending in a first direction over a substrate and forming spacers on sidewalls of the fin structure to laterally sandwiched the fin structure in a second direction. The method further includes etching the fin structure in a third direction to form a recess between the spacers and forming a doped region in the fin structure exposed by the recess. The method further includes removing an upper portion of the doped region and annealing a bottom portion of the doped region after removing the upper portion of the doped region. The method further includes forming a source/drain structure over the bottom portion of the doped region.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. MORE, Shih-Chieh CHANG, Cheng-Han LEE, Huai-Tei YANG
  • Patent number: 12021142
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 12021143
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Patent number: 12009208
    Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Yung Hung, Shahaji B. More, Chien-Feng Lin, Cheng-Han Lee, Shih-Chieh Chang, Ching-Lun Lai, Wei-Jen Lo
  • Publication number: 20240186415
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 6, 2024
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 11973127
    Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 11974367
    Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 30, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
  • Patent number: 11935955
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20240014321
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 11, 2024
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240008171
    Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.
    Type: Application
    Filed: May 4, 2023
    Publication date: January 4, 2024
    Inventors: Wei-Teng Lin, Hui-Yu Huang, Ching-Chi Chan, Shih-Chieh Chang
  • Patent number: 11855176
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 11854811
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Patent number: D1014773
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1014774
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng, Chuan-Hsi Chang
  • Patent number: D1014775
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 13, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1017061
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1017062
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Chuan-Hsi Chang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1018891
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Peng-Hui Wang, Ming-Chieh Cheng, Xiu-Yi Lin