Patents by Inventor Shih-Chieh Chang

Shih-Chieh Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11179040
    Abstract: An attachable monitoring device includes a battery unit, a flexible printed circuit board and a physical condition sensor and an adhesive. The battery unit includes a top surface, a bottom surface and a plurality of side surfaces connecting the top surface and the bottom surface. The flexible printed circuit board is bent to cover the top surface, the bottom surface and one of the side surfaces and electrically connected to the battery unit. The flexible printed circuit board includes a printed antenna printed on a first outer surface of the flexible printed circuit board. The physical condition sensor is disposed on a second outer surface of the flexible printed circuit board opposite to the first outer surface. The physical condition sensor includes a sensing region for contacting a user to detecting a physical-condition signal of the user. The adhesive is disposed on the flexible printed circuit board for being attached to the user.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 23, 2021
    Assignee: iWEECARE Co., Ltd.
    Inventors: Chun-Hao Tseng, Shih-Chien Lin, Ho-Yi Chang, Kai-Chieh Chang
  • Publication number: 20210351298
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20210351601
    Abstract: A wireless sound output device includes a wireless earbud and a charging base. The wireless earbud is placed in the charging base. If a true wireless stereo Bluetooth controller of the wireless earbud detects that a mode switching circuit of the charging base is switched to a wireless Bluetooth receiver mode, an analog signal is transmitted to an audio source output hole of the charging base through an audio source analog signal output switching unit of the wireless earbud.
    Type: Application
    Filed: June 25, 2020
    Publication date: November 11, 2021
    Inventors: PAO-CHUNG CHAO, PEI-MING CHANG, SHIH-CHIEH HSU, WEI-LUNG HUANG
  • Patent number: 11171220
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20210342767
    Abstract: An externally-connected shop floor control (SFC) system comprising M shop floor control (SFC) devices is disclosed. By letting each of the M SFC devices be electrically connected between one test machine and one information read-out device, the SFC system is successfully implemented into a production line. Therefore, each of the M SFC devices is adopted to achieve a re-verification of pass record for a test object that is transferred from a previous-stage test machine, and is also adopted for collecting related test data of the test object transferred from a current-stage test machine. As such, the SFC system can be easily implemented into any one type of production line, so as to assist the manager of the production line in data collection, station passing control, manufacturing reports, and control of production efficiency and yield, without spending much cost of human resources and software/firmware developing.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 4, 2021
    Inventors: SHIH-CHIEH HSU, WEI-LUNG HUANG, PEI-MING CHANG, PAO-CHUNG CHAO, TZU-CHI TSENG, CHIA-FENG LEE
  • Patent number: 11158757
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 26, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Yi-Chieh Lin, Shiuan-Leh Lin, Yung-Fu Chang, Shih-Chang Lee, Chia-Liang Hsu, Yi Hsiao, Wen-Luh Liao, Hong-Chi Shih, Mei-Chun Liu
  • Patent number: 11152362
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Yi-Min Huang, Shih-Chieh Chang, Tsung-Lin Lee
  • Publication number: 20210273047
    Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
    Type: Application
    Filed: July 21, 2020
    Publication date: September 2, 2021
    Inventors: Shu KUAN, Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG
  • Publication number: 20210257496
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 19, 2021
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20210257263
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: April 16, 2021
    Publication date: August 19, 2021
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun Chieh Wang
  • Patent number: 11094826
    Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Shih-Chieh Chang
  • Publication number: 20210233771
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Patent number: 11069810
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 11049945
    Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Yun-Wen Chu, Hong-Hsien Ke, Chia-Hui Lin, Shin-Yeu Tsai, Shih-Chieh Chang
  • Publication number: 20210193830
    Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20210192327
    Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 24, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Jian-Wei Su, Fu-Cheng Tsai
  • Publication number: 20210175359
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Patent number: 11031808
    Abstract: A power supply system is connected to a load, and the power supply system includes a power supply apparatus and a backup apparatus. When an input power is normal, the power supply apparatus converts the input power into a first output power, provides the first output power to the power bus, and selectively provides the first output power to charge the backup apparatus, in which the first output power has a first rated upper-limit value. When the input power is normal and a required power of the load is greater than the first rated upper-limit value, the backup apparatus provides a second output power to the power bus so that the sum of the first output power and the second output power meets the required power of the load.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: June 8, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Shih-Chieh Chang
  • Patent number: 11018176
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 11011433
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang