Patents by Inventor Shih-Chieh Chang

Shih-Chieh Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365720
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10840358
    Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 10833074
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Publication number: 20200350435
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20200338474
    Abstract: An oil-water separator with an oil discharge outlet adjusting spontaneously includes a liquid storage tank with grease and wastewater, a telescopic pipe in the liquid storage tank, and a floater unit connected with the telescopic pipe. The liquid storage tank comprises an inlet for grease and wastewater input, and a water outlet for wastewater output. The floater unit comprises at least one floater floating between grease and wastewater, and an isolation member extending in the height direction between the floater and the telescopic pipe. The isolation member fluctuates along with height changes of wastewater and includes an oil discharge outlet for grease entering the telescopic pipe. Therefore, an oil outlet, adjusting height spontaneously, is configured by the at least one floater, such that the overall height is reduced, a sufficient difference of levels of grease and wastewater is generated by the isolation member, thereby improving the oil-water separation effect.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 29, 2020
    Applicant: JENFU MACHINERY CO., LTD.
    Inventors: CHIN-LUN CHANG, CHENG-HAN CHANG, SHIH-CHIEH CHANG
  • Patent number: 10803278
    Abstract: Panel structure includes a substrate, a piezoelectric material layer and a thin film transistor. The piezoelectric material layer is disposed under the substrate, in which the piezoelectric material layer is configured to generate human recognizable sound waves by vibrating at a human audible frequency in a first time interval, and the piezoelectric material layer is configured to generate ultrasonic waves by vibrating at an ultrasonic frequency in a second time interval. The piezoelectric material layer is used for recognizing human fingerprints when it vibrates at the ultrasonic frequency. The thin film transistor is positioned under and electrically connected to the piezoelectric material layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 13, 2020
    Assignee: RECO TECHNOLOGY (CHENGDU) CO., LTD.
    Inventors: Yu-Pi Kuo, Chung-Wu Liu, Chun-Te Chang, Sin-Cheng Lin, Wan-Heng Lin, Shih-Chieh Huang
  • Publication number: 20200303548
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10785892
    Abstract: A heat dissipation system and a coolant distribution module for plural electronic components of an electronic computing device are provided. The heat dissipation system includes plural water-cooling heads, a heat dissipation device and the coolant distribution module. When a fluid medium flows through the heat dissipation device, the heat dissipation device exchanges heat with the fluid medium. The coolant distribution module is connected between the plural water-cooling heads and the heat dissipation device. The coolant distribution module includes a main body and a power module. The module main body includes a cooled fluid chamber. The cooled fluid chamber includes plural first outlets corresponding to the plural water-cooling heads. The power module is installed in the module main body. The power module drives the fluid medium to be outputted from the plural first outlets. Consequently, the fluid medium is transferred through a circulating loop.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 22, 2020
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-An Chen, Chien-Yu Chen, Mu-Shu Fan, Shih-Chieh Kao, Che-Chia Chang
  • Publication number: 20200295157
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20200273963
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium and further includes gallium in an upper portion of the epitaxial layer that is in contact with the silicide feature.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Publication number: 20200272783
    Abstract: Disclosed is an IC layout design method capable of improving the result of an IC layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Inventors: SHU-YU CHANG, SHIH-JUNG HSU, HAN-CHIEH HSIEH, YU-CHENG LO, CHENG-YU TSAI
  • Publication number: 20200266274
    Abstract: A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
  • Patent number: 10750068
    Abstract: A camera module testing method is applied to a camera module including a camera lens and a photosensitive element. In a step (A), an original image is captured through the camera lens and the photosensitive element. In a step (B), the original image is converted into a gray scale image. In a step (C), the gray scale image is converted into a binary image according to a critical gray scale value. In a step (D), a boundary contour is obtained according to plural pixels of the binary image higher than or equal to the critical gray scale value. In a step (E), a contour center of the boundary contour is obtained. Then, a step (F) is performed to judge whether an optical axis of the camera lens is aligned with an imaging center of the photosensitive element according to the imaging center and the contour center.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 18, 2020
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Pei-Ming Chang, Pao-Chung Chao, Shih-Chieh Hsu, Wei-Lung Huang
  • Patent number: 10749010
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Publication number: 20200251390
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 10734524
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200243683
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 10725898
    Abstract: An information management method for a testing network framework is provided. The testing network framework includes a first server and at least one computer. The method includes the following steps. Firstly, the at least one computer downloads and executes a test application program. Then, the at least one computer is connected to the first server, and provides a device identification code and a network address value of the at least one computer to the first server. If the first server judges that the corresponding device identification code complies with a first default condition and the corresponding network address value complies with a second default condition, the corresponding computer is authenticated, and a test setting information is provided from the first server to the corresponding computer. After the test setting information is downloaded to the corresponding computer, a test process is performed.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 28, 2020
    Assignee: PRIMAX ELECTRONICS LTD
    Inventors: Pei-Ming Chang, Pao-Chung Chao, Shih-Chieh Hsu
  • Patent number: 10720530
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20200220379
    Abstract: A power supply system is connected to a load, and the power supply system includes a power supply apparatus and a backup apparatus. When an input power is normal, the power supply apparatus converts the input power into a first output power, provides the first output power to the power bus, and selectively provides the first output power to charge the backup apparatus, in which the first output power has a first rated upper-limit value. When the input power is normal and a required power of the load is greater than the first rated upper-limit value, the backup apparatus provides a second output power to the power bus so that the sum of the first output power and the second output power meets the required power of the load.
    Type: Application
    Filed: July 5, 2019
    Publication date: July 9, 2020
    Inventor: Shih-Chieh CHANG