Abstract: A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.

Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: An antenna device comprises a substrate with an installation surface, with said substrate configured to electrically connect to a ground point; a main antenna connected to the installation surface, wherein the main antenna extends away from the installation surface, has a feeding end for receiving a signal, and is configured to form a resonance current path with the substrate to generate an original radiation field; and a reflector with a shorting end and a free end, wherein the shorting end connects to the installation surface and the reflector extends away from the installation surface; and a switch with a first end, a second end, and a control end, wherein the first end electrically connects to the free end of the reflector, the second end electrically connects to the substrate, and the control end is configured to selectively control the first end and the second end in a conductive connection.

Abstract: A dual antenna device comprises a substrate, a first antenna, a second antenna and an isolation element. The substrate comprises an installation surface, the first antenna and the second antenna protrude from the installation surface and respectively couple to the installation surface by the first grounding edge and the second grounding edge. The isolation element comprises a first isolation portion protruding from the installation surface and coupling to the installation surface by a bottom side of the first isolation portion so that the first antenna and the second antenna respectively locate at both sides of the isolation element. The first antenna and the isolation element form a first interval in the extension direction of the first grounding edge. The second antenna and the isolation element form a second interval in the extension direction of the second grounding edge. The design of the isolation element improves the isolation magnitude.

Abstract: A dual antenna device comprises a substrate, a first antenna, a second antenna and an isolation element. The substrate comprises an installation surface, the first antenna and the second antenna protrude from the installation surface and respectively couple to the installation surface by the first grounding edge and the second grounding edge. The isolation element comprises a first isolation portion protruding from the installation surface and coupling to the installation surface by a bottom side of the first isolation portion so that the first antenna and the second antenna respectively locate at both sides of the isolation element. The first antenna and the isolation element form a first interval in the extension direction of the first grounding edge. The second antenna and the isolation element form a second interval in the extension direction of the second grounding edge. The design of the isolation element improves the isolation magnitude.

Abstract: An electronic assembly includes a heat generating element, a heat dissipation fin set and a filter circuit board. The filter circuit board is disposed between the heat generating element and the heat dissipation fin set. The filter circuit board includes a metal layer, an electromagnetic band gap structure layer, an insulation layer disposed between the metal layer and the electromagnetic band gap structure layer and plural first thermal vias. The heat dissipation fin set is disposed on the heat generating element and directly contacts the metal layer. The electromagnetic band gap structure layer has plural conductive patterns arranged in the same pitches. The heat generating element directly contacts at least one of the conductive patterns. The first thermal vias pass through the insulation layer, the metal layer and the conductive patterns. Two ends of each first thermal via respectively connect the metal layer and the corresponding conductive pattern.

Abstract: A planar magnetic field probe is provided. The planar magnetic field probe increases the sensitivity of magnetic field intensity detection by using a left multi-sensor loop and a right multi-sensor loop formed by a first patterned metal layer and a second patterned metal layer, and decreases the electric field noise coupling by surrounding the left multi-sensor loop and the right multi-sensor loop with a symmetrical shielding metal structure formed by a first patterned shielding metal layer, a second patterned shielding metal layer and a plurality of through vias.

Abstract: An electronic assembly includes a heat generating element, a heat dissipation fin set and a filter circuit board. The filter circuit board is disposed between the heat generating element and the heat dissipation fin set. The filter circuit board includes a metal layer, an electromagnetic band gap structure layer, an insulation layer disposed between the metal layer and the electromagnetic band gap structure layer and plural first thermal vias. The heat dissipation fin set is disposed on the heat generating element and directly contacts the metal layer. The electromagnetic band gap structure layer has plural conductive patterns arranged in the same pitches. The heat generating element directly contacts at least one of the conductive patterns. The first thermal vias pass through the insulation layer, the metal layer and the conductive patterns. Two ends of each first thermal via respectively connect the metal layer and the corresponding conductive pattern.

Abstract: A planar magnetic field probe is provided. The planar magnetic field probe increases the sensitivity of magnetic field intensity detection by using a left multi-sensor loop and a right multi-sensor loop formed by a first patterned metal layer and a second patterned metal layer, and decreases the electric field noise coupling by surrounding the left multi-sensor loop and the right multi-sensor loop with a symmetrical shielding metal structure formed by a first patterned shielding metal layer, a second patterned shielding metal layer and a plurality of through vias.

Abstract: A circuit board structure includes a dielectric layer, a first metal layer, a second metal layer and a first ferrite element. The first metal layer is disposed on an upper surface of the dielectric layer and has a first circuit area, a second circuit area and a first metallic neck connecting the first circuit and the second circuit areas. The second metal layer is disposed on a lower surface of the dielectric layer and has a third circuit area, a fourth circuit area and at least a second metallic neck connecting the third circuit and the fourth circuit areas. The orthogonal projections of the first and the second metallic necks on the upper surface are not overlapped. The first ferrite element is disposed on the upper surface and overlays at least one of the orthogonal projections of the first and the second metallic necks on the upper surface.

Abstract: A circuit board including a first patterned metal layer and a second patterned metal layer is provided. The first patterned metal layer has metal blocks and spiral structures. A gap is kept between any two adjacent metal blocks. Each of the spiral structures is electrically connected between any two adjacent metal blocks. The second patterned metal layer is disposed beside the first patterned metal layer and has jumper segments. Each of the jumper segments has a first end and a second end opposite to the first end. Each of the spiral structures has an outer end and an inner end. The outer end is connected to one of the two adjacent metal blocks. The inner end is electrically connected to the first end of one of the jumper segments, and the second end of the jumper segment is electrically connected to the other one of the two the metal blocks.

Abstract: A measurement correcting system including a field measuring unit and a processing unit is provided. The field measuring unit simultaneously senses a first signal to be measured and a second signal to be measured which have opposite polarities and substantially the same magnitude, and generates a first output signal and a second output signal correspondingly. The processing unit determines the first signal to be measured according to the first output signal and the second output signal. A measurement correcting method is also provided.

Abstract: A circuit board structure includes a dielectric layer, a first metal layer, a second metal layer and a first ferrite element. The first metal layer is disposed on an upper surface of the dielectric layer and has a first circuit area, a second circuit area and a first metallic neck connecting the first circuit and the second circuit areas. The second metal layer is disposed on a lower surface of the dielectric layer and has a third circuit area, a fourth circuit area and at least a second metallic neck connecting the third circuit and the fourth circuit areas. The orthogonal projections of the first and the second metallic necks on the upper surface are not overlapped. The first ferrite element is disposed on the upper surface and overlays at least one of the orthogonal projections of the first and the second metallic necks on the upper surface.

Abstract: A circuit board including a first patterned metal layer and a second patterned metal layer is provided. The first patterned metal layer has metal blocks and spiral structures. A gap is kept between any two adjacent metal blocks. Each of the spiral structures is electrically connected between any two adjacent metal blocks. The second patterned metal layer is disposed beside the first patterned metal layer and has jumper segments. Each of the jumper segments has a first end and a second end opposite to the first end. Each of the spiral structures has an outer end and an inner end. The outer end is connected to one of the two adjacent metal blocks. The inner end is electrically connected to the first end of one of the jumper segments, and the second end of the jumper segment is electrically connected to the other one of the two the metal blocks.

Abstract: A structure of a multi-layer printed circuit board includes a power layer, a ground layer, and a dielectric layer. The dielectric layer is located between the power layer and the ground layer. The dielectric layer has a relative permittivity and a relative permeability, wherein the product of the relative permittivity and the relative permeability substantially decreases along with an increase in frequency within a frequency range.

Abstract: A low noise multilayer printed circuit board includes at least one ground layer and at least one power layer. The at least one ground layer is divided into a first area and a second area. The first area and the second area are connected by a first metal neckline. The at least one power layer is divided into a third area and a fourth area. The third area and the fourth area are connected by a second metal neckline. The first area corresponds to the third area. The second area corresponds to the fourth area. The location where the first and second areas are connected by the first metal neckline is different from that where the third and fourth areas are connected by the second metal neckline.

Abstract: A signal transmission structure is provided. The signal transmission structure includes conduction blocks periodically formed at a power plane, neck blocks connecting adjacent conduction blocks, and openings formed corresponding to the neck blocks at a ground plane for reducing equivalent capacitance between the neck blocks and the ground plane, so as to improve the noise isolation performance.

Abstract: A method for suppressing the resonant effect between capacitors connected in parallel is disclosed. By adjusting the length of the transmission line of the shunt capacitors, the performance of the shunt capacitors, which can be applied on various types of filtering circuits, can be improved in the desired bandwidth.