Abstract: An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.

Abstract: An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract: A semiconductor device includes a substrate; a deep well region disposed in the substrate; an element region disposed in the substrate and in the deep well region; a drain region disposed in the substrate, in the deep well region, and surrounding the element region; a gate structure disposed on the surface of the substrate, adjacent to the deep well region, and surrounding the drain region; a well region disposed in the substrate, in the deep well region, and surrounding the gate structure; a source region disposed in the substrate, in the well region, and surrounding the gate structure; a body contact region disposed separately from the source region in the well region and surrounding the source region; and an annular doped region disposed separately from the deep well region in the substrate and surrounding the deep well region.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate including a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region including a second conductivity type, and a source region formed in the substrate, where the source region includes at least one first part and at least one second part, the first part includes the second conductivity type, the second part includes the first conductivity type, and the first conductivity type and the second conductivity type are complementary.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate, a gate positioned on the substrate, a drain region formed in the substrate, a source region formed in the substrate, a first doped region formed in between the drain region and the source region, and a second doped region formed over a top of the first doped region or/and under a bottom of the first doped region. The drain region, the source region, and the second doped region include a first conductivity type, the first doped region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary.

Abstract: A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.

Abstract: A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.

Abstract: Deep trench isolation structures between high voltage semiconductor devices and fabrication methods thereof are presented.

Abstract: A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region.

Abstract: A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region.