Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A hierarchical mechanism for preventing concentrated wear on single physical block or a specific set of physical blocks in the physical memory is proposed. The logical blocks mapping to the physical blocks in the physical memory are classified into two different levels for implicitly representing the modification times of the physical blocks. A modify count and a maximum modify count are further included for counting the modification times in a single process of the hierarchical mechanism and for limiting the modification times in single process, leading to the probabilities of all the physical blocks being modified in the physical memory being balanced. The breakdown of the physical memory caused by the breakdown of a specific set of physical blocks or single physical block is thus prevented.

Abstract: A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.

Abstract: A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands.

Abstract: A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone.

Abstract: According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows 0, 1, 2 and 3, the logical block addresses comprise logical block addresses 0, 1, 2 and 3, and logical block addresses 0, 1, 2 and 3 point to Windows 0, 1, 2 and 3, respectively.

Abstract: A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

Abstract: A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.

Abstract: A method for copying data in a non-volatile memory system is disclosed. The method includes calculating a number of errors of a first set of data from a source block of the non-volatile memory saved in the buffer of the controller, transmitting the first set of data saved in the buffer of the controller to a buffer of the non-volatile memory when the number of errors is lower than a threshold, and programming a destination block of the non-volatile memory with the first set of data saved in the buffer of the non-volatile memory when the number of errors is lower than the threshold.

Abstract: A hierarchical mechanism for preventing concentrated wear on single physical block or a specific set of physical blocks in the physical memory is proposed. The logical blocks mapping to the physical blocks in the physical memory are classified into two different levels for implicitly representing the modification times of the physical blocks. A modify count and a maximum modify count are further included for counting the modification times in a single process of the hierarchical mechanism and for limiting the modification times in single process, leading to the probabilities of all the physical blocks being modified in the physical memory being balanced. The breakdown of the physical memory caused by the breakdown of a specific set of physical blocks or single physical block is thus prevented.

Abstract: A flash memory configuration and access method having a particular conversion method that uses the page or the sector in each flash memory block instead of the block that is commonly used as the base of the data conversion storage to store data. When data is written into the physical flash block of the flash memory, the original logic sector information can be preserved. The data is written into the same block of the flash memory in a manner according to the sequence as it is received instead of the sequence of the logic sector. Therefore, the block position does not move to refresh the block content until the physical block is full. Consequently, the number of times to move the physical block of the flash memory can be reduced to increase the lifetime of the flash memory. Moreover, since the number of times to erase is reduced, so that the writing speed can speed up to improve the operation efficiency.

Abstract: A flash memory configuration and access method having a particular conversion method that uses the page or the sector in each flash memory block instead of the block that is commonly used as the base of the data conversion storage to store data. When data is written into the physical flash block of the flash memory, the original logic sector information can be preserved. The data is written into the same block of the flash memory in a manner according to the sequence as it is received instead of the sequence of the logic sector. Therefore, the block position does not move to refresh the block content until the physical block is full. Consequently, the number of times to move the physical block of the flash memory can be reduced to increase the lifetime of the flash memory. Moreover, since the number of times to erase is reduced, so that the writing speed can speed up to improve the operation efficiency.