Patents by Inventor Shih Chih Wong

Shih Chih Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6967392
    Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: November 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chieh Tsai, Shih Chih Wong
  • Publication number: 20030122235
    Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.
    Type: Application
    Filed: February 19, 2003
    Publication date: July 3, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chao-Chieh Tsai, Shih Chih Wong
  • Patent number: 6537849
    Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: March 25, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Chieh Tsai, Shih Chih Wong