Patents by Inventor Shih-Chin Lee
Shih-Chin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20240087207Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Applicant: MediaTek Inc.Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
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Publication number: 20230380174Abstract: An integrated circuit structure includes a substrate, a conductive layer, a plurality of memory devices, a bonding pad, and a source line. The conductive layer is over the substrate. The memory devices are stacked in a vertical direction over the conductive layer. The bonding pad is over the conductive layer. The source line extends upwardly from the bonding pad and has a lower portion inlaid in the bonding pad and an upper portion having a sidewall coterminous with a sidewall of the bonding pad. A top end of the source line has a first lateral dimension greater than a second lateral dimension of the bonding pad.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Li-Wei WANG, Hong-Ji LEE, Fu-Xing ZHOU, Shih-Chin LEE
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Publication number: 20230187359Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Patent number: 11610842Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: GrantFiled: December 2, 2020Date of Patent: March 21, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Publication number: 20220173040Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
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Patent number: 9748332Abstract: A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension, in which each memory cell of the multiple memory cells includes a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, and a first electrode layer on the tunnel dielectric layer. Along the first dimension, the channel region of each memory cell of the multiple memory cells is separated from the channel region of an adjacent memory cell of the multiple memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate up to an inter-electrode dielectric layer.Type: GrantFiled: December 9, 2016Date of Patent: August 29, 2017Assignee: Macronix International Co., Ltd.Inventors: Chih Kai Yang, Chen Yu Cheng, Shih Chin Lee, Ching Hung Wang, Tzung-Ting Han
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Patent number: 8466508Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.Type: GrantFiled: October 3, 2007Date of Patent: June 18, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Shaw-Hung Ku, Shih-Chin Lee, Chia-Wei Wu, Shang-Wei Lin, Tzung-Ting Han, Ming-Shang Chen, Wen-Pin Lu
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Patent number: 8026136Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3Ă—1011/cm?2, and methods for forming such memory cells.Type: GrantFiled: December 26, 2007Date of Patent: September 27, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Yen-Hao Shih, Min-Ta Wu, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Publication number: 20110047061Abstract: A method for detecting abnormal transactions of a financial asset and an information processing device performing the method are disclosed. The method is used for detecting whether a plurality of account data have a abnormal transaction, and the method comprises the steps of: receiving historic information, wherein the historic information comprises the account data and each number of trades made on each transaction day of each account within a period; establishing a plurality of information matrixes; choosing two of the plurality of information matrixes for making an inner product operation and acquiring an inner product value; constructing the threshold of the inner product value; determining whether the inner product value is greater than the threshold of the inner product value; and if yes, determining the two corresponding accounts of the information matrixes having the abnormal transaction.Type: ApplicationFiled: June 29, 2010Publication date: February 24, 2011Inventors: Shih-Chin Lee, Hwai-Chung Ho, Hong-Wei Chuang
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Patent number: 7888272Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.Type: GrantFiled: December 12, 2006Date of Patent: February 15, 2011Assignee: Macronix International Co. Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Tzung Ting Han, Ming-Shang Chen, Shih Chin Lee
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Patent number: 7889556Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.Type: GrantFiled: January 20, 2010Date of Patent: February 15, 2011Assignee: Macronix International Co., Ltd.Inventors: Shaw Hung Ku, Ten Hao Yeh, Shih Chin Lee, Shang Wei Lin, Chia Wei Wu, Tzung Ting Han, Ming Shang Chen, Wenpin Lu
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Patent number: 7824991Abstract: A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.Type: GrantFiled: January 18, 2006Date of Patent: November 2, 2010Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Shih-Chin Lee
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Patent number: 7763935Abstract: A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.Type: GrantFiled: June 23, 2005Date of Patent: July 27, 2010Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh
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Publication number: 20100120210Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.Type: ApplicationFiled: January 20, 2010Publication date: May 13, 2010Applicant: Macronix International Co., Ltd.Inventors: SHAW-HUNG KU, Ten Hao Yeh, Shih Chin Lee, Shang Wei Lin, Chia Wei Wu, Tzung Ting Han, Ming Shang Chen, Wenpin Lu
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Patent number: 7704865Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.Type: GrantFiled: August 23, 2005Date of Patent: April 27, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Yen-Hao Shih, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Patent number: 7668010Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.Type: GrantFiled: February 27, 2008Date of Patent: February 23, 2010Assignee: Macronix International Co., Ltd.Inventors: Shaw Hung Ku, Ten Hao Yeh, Shih Chin Lee, Shang Wei Lin, Chia Wei Wu, Tzung Ting Han, Ming Shang Chen, Wenpin Lu
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Publication number: 20090213656Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Applicant: Macronix International Co., Ltd.Inventors: Shaw Hung Ku, Teng Hao Yeh, Shih-Chin Lee, Shang-Wei Lin, Chia-Wei Wu, Tzung Ting Han, Ming Shang Chen, Wenpin Lu
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Publication number: 20090091983Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Shih-Chin Lee, Chia-Wei Wu, Shang-Wei Lin, Tzung-Ting Han, Ming-Shang Chen, Wen-Pin Lu
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Patent number: 7453127Abstract: A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.Type: GrantFiled: February 13, 2006Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Feng-Chi Hung, Hung-Lin Chen, Shih-Chin Lee