Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.

Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high voltage threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high voltage threshold voltage channel region is formed in the first well and extending down from the surface of the substrate.

Abstract: A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type and disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a deep implantation region having the first conductivity type and disposed in the high-voltage well between the source well and the drift region.

Abstract: A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.

Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall.

Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.

Abstract: A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall.

Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Abstract: An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type and disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a deep implantation region having the first conductivity type and disposed in the high-voltage well between the source well and the drift region.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first conductive type, forming a high-voltage well having a second conductive type in the substrate, forming a drift region in the high-voltage well, and forming an insulation layer on the substrate. The insulation layer includes a first insulation portion and a second insulation portion respectively covering opposite edge portions of the drift region, and not covering a top portion of the drift region.

Abstract: A semiconductor device includes a substrate, an insulation layer disposed over the substrate, covering a drift region, and including a first edge and a second edge opposite to the first edge, a gate layer covering the first edge of the insulation layer, and a metal layer including a metal portion connected to the gate layer and overlapping the first edge of the insulation layer. The metal portion includes a first edge located closer to a central portion of the insulation layer than an opposite second edge of the metal portion. A distance from the first edge of the metal portion to the first edge of the insulation layer along a channel length direction is a. A distance from the first edge of the insulation layer to the second edge of the insulation layer is L. A ratio of a/L is equal to or higher than 0.46.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate structure, source and drain regions and a conductive layer. The source and drain regions are disposed in the substrate. The isolation structure is disposed between the source and drain regions. The gate structure is disposed on the substrate between the source and drain regions. The conductive layer is disposed on the substrate, extends from above the source region to above the isolation structure and is electrically connected to the source region. The substrate has first and second areas. The source region in the second area has a border curvature greater than that in the first area. The width of the portion of the conductive layer covering the isolation structure in the second area has a width greater than that in the first area.