Patents by Inventor Shih-Ching Chen

Shih-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240128376
    Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 11852679
    Abstract: A circuit board for semiconductor test includes first and second sub-circuit boards, and an insulating dielectric layer therebetween. Each sub-circuit board includes a substrate and circuits including upper and lower contacts. The insulating dielectric layer includes through holes, and connecting conductors disposed therein and electrically connected with the upper and lower contacts of two sub-circuit boards. The circuit board is defined with central and peripheral regions. The lower contacts of the first sub-circuit board in the central region are electrically connected with a probe head. The upper contacts of the second sub-circuit board in the peripheral region are electrically connected with a tester, larger in pitch than the lower contacts of the first sub-circuit board in the central region, and larger in amount than the lower contacts of the first sub-circuit board in the peripheral region. The circuit board has great power test uniformity.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 26, 2023
    Assignee: MPI CORPORATION
    Inventors: Shih-Ching Chen, Jun-Liang Lai, Shung-Bo Lin, Ta-Cheng Liao, Yu-Chih Hsiao, Kun-Han Hsieh
  • Patent number: 11612744
    Abstract: A head cap with channel identification includes a head cap, channel identification module, a controlling module, and electrical stimulation modules. The head cap includes the channels therein, and the head cap includes brain regions corresponding to the brain areas of the human being. The electrical stimulation modules disposed in the channels, and the channel identification modules disposed around the peripheral of the channels. The controlling module is electrically coupled to the channel identification modules. When the electrical stimulation modules disposed in some of the channels, the channel identification modules around the peripheral of the channels and the electrical stimulation module are constituted a circuit conduction status or a short circuit status, then the channel identification module transmits a signal to the controlling module to determine the desired sites of the electrical stimulation module where is corresponding to one of the brain areas of the human being according to the signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 28, 2023
    Assignees: TAIPEI MEDICAL UNIVERSITY, NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Shih-Ching Chen, Chih-Wei Peng, Che-Wei Lin, Jia-Jin Chen, Chun-Wei Wu, Samuel Wang, Chun-Ie Wu, Nguyen Van Truong
  • Patent number: 11513638
    Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 29, 2022
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Yeh-Sheng Wang, Wei-Chia Fang, Chun-Hung Chu, Chung-Chin Hsiao, Ya-Ting Lin, Shih-Ching Chen
  • Publication number: 20220334178
    Abstract: A circuit board for semiconductor test includes first and second sub-circuit boards, and an insulating dielectric layer therebetween. Each sub-circuit board includes a substrate and circuits including upper and lower contacts. The insulating dielectric layer includes through holes, and connecting conductors disposed therein and electrically connected with the upper and lower contacts of two sub-circuit boards. The circuit board is defined with central and peripheral regions. The lower contacts of the first sub-circuit board in the central region are electrically connected with a probe head. The upper contacts of the second sub-circuit board in the peripheral region are electrically connected with a tester, larger in pitch than the lower contacts of the first sub-circuit board in the central region, and larger in amount than the lower contacts of the first sub-circuit board in the peripheral region. The circuit board has great power test uniformity.
    Type: Application
    Filed: April 14, 2022
    Publication date: October 20, 2022
    Applicant: MPI CORPORATION
    Inventors: SHIH-CHING CHEN, JUN-LIANG LAI
  • Publication number: 20220301739
    Abstract: An optically consistent transparent conductor includes a first region and a second region. The first region includes a plurality of nanostructures. The first region has a first electrical resistivity and a first haze. The second region has a second electrical resistivity and a second haze. A difference in ratio between the first electrical resistivity and the second electrical resistivity is in a range from 5% to 9900%, and a difference in ratio between the first haze and the second haze is in a range from 2% to 500%.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Shih-Ching Chen, Wei-Chia Fang, En-Chia Chang, Wei-Cheng Hsu, Chung-Chin Hsiao
  • Publication number: 20220197415
    Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Yeh-Sheng Wang, Wei-Chia Fang, Chun-Hung Chu, Chung-Chin Hsiao, Ya-Ting Lin, Shih-Ching Chen
  • Patent number: 11353996
    Abstract: Covers for touch-sensing devices include a shielding layer; and a substrate, in which the substrate covers the shielding layer, and the substrate and the shielding layer are integrated and form a coplanar surface. The coplanar surface is a smooth surface, which has a surface roughness Ra in a range from about 0.05 ?m to about 0.5 ?m.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 7, 2022
    Assignee: TPK Universal Solutions Limited
    Inventors: Shun-Jie Yang, Shih-Ching Chen, Chen-Hui Cheng
  • Patent number: 11249572
    Abstract: A touch panel is provided, including a substrate, a first wire structure, and a second wire structure. The substrate includes a display area and a peripheral area surrounding the display area. The first wire structure includes a first catalyst layer, a first metal layer, and a first transparent conductive layer. The first catalyst layer is disposed above the peripheral area, the first metal layer is disposed above the first catalyst, and the first transparent conductive layer is disposed above the first metal layer. The first wire structure is divided into at least one first wire area and at least one first ground line area adjacent to the first wire area. The second wire structure is disposed under the peripheral area and includes at least one second ground line area, wherein a projection of the first wire area in a vertical direction is opposite to the second ground line area.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: February 15, 2022
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Shih-Ching Chen, Wei-Chia Fang, Chun-Hung Chu, Chung-Chin Hsiao
  • Publication number: 20210357054
    Abstract: A touch panel is provided, including a substrate, a first wire structure, and a second wire structure. The substrate includes a display area and a peripheral area surrounding the display area. The first wire structure includes a first catalyst layer, a first metal layer, and a first transparent conductive layer. The first catalyst layer is disposed above the peripheral area, the first metal layer is disposed above the first catalyst, and the first transparent conductive layer is disposed above the first metal layer. The first wire structure is divided into at least one first wire area and at least one first ground line area adjacent to the first wire area. The second wire structure is disposed under the peripheral area and includes at least one second ground line area, wherein a projection of the first wire area in a vertical direction is opposite to the second ground line area.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 18, 2021
    Inventors: Shih-Ching Chen, Wei-Chia Fang, Chun-Hung Chu, Chung-Chin Hsiao
  • Publication number: 20210213285
    Abstract: A head cap with channel identification includes a head cap, channel identification module, a controlling module, and electrical stimulation modules. The head cap includes the channels therein, and the head cap includes brain regions corresponding to the brain areas of the human being. The electrical stimulation modules disposed in the channels, and the channel identification modules disposed around the peripheral of the channels. The controlling module is electrically coupled to the channel identification modules. When the electrical stimulation modules disposed in some of the channels, the channel identification modules around the peripheral of the channels and the electrical stimulation module are constituted a circuit conduction status or a short circuit status, then the channel identification module transmits a signal to the controlling module to determine the desired sites of the electrical stimulation module where is corresponding to one of the brain areas of the human being according to the signal.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 15, 2021
    Inventors: Shih-Ching CHEN, Chih-Wei PENG, Che-Wei LIN, Jia-Jin CHEN, Chun-Wei WU, Samuel WANG, Chun-Ie WU, Nguyen Van TRUONG
  • Patent number: 11050207
    Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 29, 2021
    Assignee: Securitag Assembly Group Co., Ltd.
    Inventors: Tung -Sheng Chen, Shih- Ching Chen, Chih- Cheng Chuang
  • Publication number: 20200176940
    Abstract: A crimping apparatus comprising a press module connected with a pressing mold, a translation module, and a pressure control module is disclosed. The press module generates an action force on the pressing mold through a fluid. The translation module is coupled to the press module for driving the press module to move toward a flexible printed circuit having two isolated circuit layers such that one circuit layer is pressed to crimp to the other circuit layer, wherein the pressure control module adjusts the pressure within the press module to maintain a constant force on the pressing mold whereby the pressing mold can generate a constant stress acting on the flexible printed circuit during the crimping process. In addition, the crimping apparatus can be adapted in a roll-to-roll process for crimping two isolated circuit layers of each flexible printed circuit unit arranged on the roll.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Securitag Assembly Group Co., Ltd.
    Inventors: Tung -Sheng Chen, Shih- Ching Chen, Chih- Cheng Chuang
  • Publication number: 20200117293
    Abstract: Covers for touch-sensing devices include a shielding layer; and a substrate, in which the substrate covers the shielding layer, and the substrate and the shielding layer are integrated and form a coplanar surface. The coplanar surface is a smooth surface, which has a surface roughness Ra in a range from about 0.05 ?m to about 0.5 ?m.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 16, 2020
    Inventors: Shun-Jie YANG, Shih-Ching CHEN, Chen-Hui CHENG
  • Patent number: 10543367
    Abstract: The invention provides transcranial electrostimulation by combining transcranial direct current stimulation (tDCS) and theta burst stimulation (TBS) to achieve an unexpected therapeutic effect in various brain or neural diseases. Accordingly, the invention provides a mode of direct current with biphasic square wave pulses in the treatment of brain or neural diseases. Also provided are methods of employing the transcranial electrostimulation of the invention and applications of the transcranial electrostimulation of the invention.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 28, 2020
    Assignees: TAIPEI MEDICAL UNIVERSITY, NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chih-Wei Peng, Shih-Ching Chen, Yu Ting Li, Hsiang Ching Lee, Jia-Jin J. Chen, Tsung-Hsun Hsieh, Chien-Hung Lai, Jiunn-Horng Kang
  • Patent number: 10461002
    Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
  • Patent number: 10434707
    Abstract: A touch substrate manufactured by three-dimensional printing and a method for manufacturing the same are disclosed. The method for manufacturing the touch substrate works together with a three-dimensional printer. The three-dimensional printer includes a first nozzle, a second nozzle, and a light source. The method includes the steps of: jetting a photocuring material by the first nozzle and exposing the photocuring material to the light source to form a base layer; jetting a conductive material on the base layer by the second nozzle and exposing the conductive material to the light source to form a touch electrode layer; and jetting the photocuring material on the base layer and the touch electrode layer by the first nozzle and exposing the photocuring material to the light source to form a protective layer. The touch electrode layer is embedded between the base layer and the protective layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 8, 2019
    Assignee: TPK Universal Solutions Limited
    Inventors: Shun-Jie Yang, Shun-Ta Chien, Shih-Ching Chen, Wen-Fu Huang