Patents by Inventor Shih-Ching Yang

Shih-Ching Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 10026603
    Abstract: A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 17, 2018
    Assignee: PHOENIX SILICON INTERNATIONAL CORP.
    Inventors: Shih-Ching Yang, Chien-Hsiung Huang, Chao-Tsung Tsou, Cheng-Yen Lin
  • Publication number: 20170372885
    Abstract: A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 28, 2017
    Inventors: SHIH-CHING YANG, CHIEN-HSIUNG HUANG, CHAO-TSUNG TSOU, CHENG-YEN LIN
  • Publication number: 20040019172
    Abstract: The present invention relates to a method for the production of a biodegradable, water absorbable resin, by directly cross-linking of a culture broth with a cross-linker. The cross-linker contains two or more functional groups in the same molecule which can react with the functional groups in the culture broth. The present invention further relates to a biodegradable, water absorbable resin and its uses.
    Type: Application
    Filed: December 12, 2002
    Publication date: January 29, 2004
    Applicant: Tou-Hsiung Yang
    Inventors: Kun-Hsiang Yang, Shih-Ching Yang, Yuan-Chi Su, Toshio Hara