Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.

Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.

Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.

Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Abstract: Various embodiments are directed to a mechanism for reserving power resources to address non-uniform and complex routings on a redistribution layer of a flip-chip. Reserving power resources may be performed by rerouting RDL nets by, for example, identifying an initial RDL net route for a RDL net; defining an outer boundary relative to the initial RDL net route, wherein a perimeter of the outer boundary is defined at a defined distance away from the initial RDL net route; defining one or more blockages extending from bumps to intersect the outer boundary; subdividing the initial RDL net route into a plurality of net portions, wherein each net portion is bounded by a portion of the outer boundary and one or more of the blockages; and rerouting at least one of the plurality of net portions to be adjacent at least one blockage bounding the circuit net portion.

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract: A power amplifier without transformer includes an audio isolator, a phase detector, a power protection controller, a rectifier and an amplifier. The audio isolator is used to isolate audio-source input end and the amplifier for making the amplifier directly connected to utility power via the rectifier without transformer to increase transformation efficiency and decrease weight and bulk of the power amplifier substantially. The phase detector is used to detect utility power phase whether correct. The power protection controller is used to determine utility power whether supply to the amplifier for preventing the amplifier from broken caused by excessive current.

Abstract: A power amplifier without transformer includes an audio isolator, a phase detector, a power protection controller, a rectifier and an amplifier. The audio isolator is used to isolate audio-source input end and the amplifier for making the amplifier directly connected to utility power via the rectifier without transformer to increase transformation efficiency and decrease weight and bulk of the power amplifier substantially. The phase detector is used to detect utility power phase whether correct. The power protection controller is used to determine utility power whether supply to the amplifier for preventing the amplifier from broken caused by excessive current.

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

Abstract: A chemical vapor deposition apparatus for titanium-nitride application that is useful for preventing contaminants caused by arching between a substantially planar substrate and a substrate supporting apparatus during the deposition cycle. The apparatus includes a chemical vapor deposition chamber having a substrate-supporting heater. An annular housing supported by the heater, and a conductive strap that connectively secures the substrate-supporting heater to the annular housing by using holes instead of conventional slots. The conductive strap is designed as a flexure to flex with process temperature changes to improve electrical connectivity at its terminal connection and to prevent degradation. The annular housing has a top and a bottom surface and a cylindrical wall extending peripherally below the surfaces. The cylindrical wall encircles an isolator ring.

Abstract: A lockable wheel coupling comprises an axle plate having a splined shaft with a central bore, a wheel having a fluted axial bore, and a generally cylindrical locking member. The wheel can be mounted on the axle plate by engaging the shaft thereon with the axial bore of the wheel. Spring biased and radially displaceable retaining lugs within the central bore are engaged with retaining recesses on the inner periphery of the axial bore via aligned apertures in the shaft upon insertion of the locking member into the central bore, to releasably secure the wheel to the axle plate. The locking member carries a cam surface for displacing the retaining lugs outwards into corresponding retaining recesses and a set of locking bolts that snap engage into an annular locking recess in the inner periphery of the central bore to retain the locking member therein. A key operated lock cylinder within the locking member retracts the bolts when rotated so that the member can be removed from the central bore.