Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Abstract: The present invention discloses a detection device and a probe module thereof, wherein an electrical connection path between a battery detection frame and a battery under test is provided via the probe module. The probe module includes a base, a first polarity plate, a second polarity plate, a first upper connection group, a second upper connection group, a first lower connection member and a second lower connection member. Via the first polarity plate, the first upper connection group is correspondingly coupled to the battery detection frame, and the first lower connection member is correspondingly coupled to the battery under test. Via the second polarity plate, the second upper connection group is correspondingly coupled to the battery detection frame, and the second lower connection member is correspondingly coupled to the battery under test. Thus, it is not necessary to process a cable having been fixed on the battery detection frame when the probe module is replaced.

Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.

Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Abstract: The present disclosure provides satellite tracking systems and tracking methods. The satellite tracking system includes an array of antenna elements and a control unit. A feed current for each of the antenna elements passes through a phase shifter. The control unit generates a control signal for the phase shifter. The satellite tracking system searches, positions, and tracks a target satellite in accordance with the control signal. The satellite tracking systems and methods utilize step scanning and particle swarm optimization in the search stage, compensating for gaps formed during the satellite searching in the positioning stage, and conical scanning in the tracking stage.

Abstract: A control method for a flash memory, a flash memory die and the flash memory are provided. The control method includes: in a setup stage, under an operation mode of a command input, issuing by a host a setup command to map each port of an external data bus of each flash memory die respectively to a status index of each flash memory die; and in a request stage, under the operation mode of the command input, issuing by the host a request command to each flash memory die, and under the operation mode of a data output, a status of the status index of each flash memory die is transmitted to the host through the ports of the external data bus respectively.

Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: The present disclosure provides satellite tracking systems and tracking methods. The satellite tracking system includes an array of antenna elements and a control unit. A feed current for each of the antenna elements passes through a phase shifter. The control unit generates a control signal for the phase shifter. The satellite tracking system searches, positions, and tracks a target satellite in accordance with the control signal. The satellite tracking systems and methods utilize step scanning and particle swarm optimization in the search stage, compensating for gaps formed during the satellite searching in the positioning stage, and conical scanning in the tracking stage.

Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: A control method for flash memory, a flash memory die and a flash memory are provided. The control method comprises: in a setup stage, under an operation mode of command input, issuing by a host a setup command to map each port of an external data bus of each flash memory die respectively to a status index of each flash memory die; and in a request stage, under the operation mode of command input, issuing by the host a request command to each flash memory dies, and under the operation mode of data output, status of the status index of each flash memory die is transmitted to the host through the ports of the data bus respectively.

Abstract: Method and apparatus for improving continuous read operations with expanded serial interface are provided. In one aspect, a device comprises: a memory configured to store data; a buffer configured to receive data from outside of the device and transfer the received data to the memory; a plurality of input pins configured to be coupled to an expanded serial peripheral interface (xSPI); and a processor configured to: select a slave device, through the xSPI, from a plurality of slave devices, send instruction data to the slave device for data reading, receive data, through the xSPI, from the selected slave device, and receive a signal on a data strobe line of the xSPI and determine data reading operations based on the received signal.

Abstract: Method and apparatus for improving continuous read operations with expanded serial interface are provided. In one aspect, a device comprises: a memory configured to store data; a buffer configured to receive data from outside of the device and transfer the received data to the memory; a plurality of input pins configured to be coupled to an expanded serial peripheral interface (xSPI); and a processor configured to: select a slave device, through the xSPI, from a plurality of slave devices, send instruction data to the slave device for data reading, receive data, through the xSPI, from the selected slave device, and receive a signal on a data strobe line of the xSPI and determine data reading operations based on the received signal.

Abstract: A heat dissipating fin assembly includes a bottom, a plurality of first heat dissipating fins, a plurality of second heat dissipating fins, an inner cover and an outer cover. The first heat dissipating fins extend from an inner end toward an outer end. The second heat dissipating fins are arranged between two of the first heat dissipating fins in staggered. The inner cover is disposed near the inner end and connected to the first heat dissipating fins. The outer cover is disposed near the outer end and connected to the second heat dissipating fins. The inner cover and the outer cover are separated to form an opening, and the dusts entering the heat dissipating fin assembly through the inner end are ejected via the opening. The second heat dissipating fins extend from around the opening to the outer end.

Abstract: A heat dissipating fin assembly includes a bottom, a plurality of first heat dissipating fins, a plurality of second heat dissipating fins, an inner cover and an outer cover. The first heat dissipating fins extend from an inner end toward an outer end. The second heat dissipating fins are arranged between two of the first heat dissipating fins in staggered. The inner cover is disposed near the inner end and connected to the first heat dissipating fins. The outer cover is disposed near the outer end and connected to the second heat dissipating fins. The inner cover and the outer cover are separated to form an opening, and the dusts entering the heat dissipating fin assembly through the inner end are ejected via the opening. The second heat dissipating fins extend from around the opening to the outer end.

Abstract: A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.

Abstract: A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.

Abstract: A method for reading data from memory cells of a target word line in a semiconductor memory includes determining a disturbance status of the target word line. The disturbance status reflects a disturbance of a neighboring word line on the memory cells of the target word line. The method further includes determining a read voltage for the target word line according to the disturbance status of the target word line and applying the read voltage to the memory cells of the target word line.