Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.

Abstract: A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical solution. The method further includes detecting the concentration of at least one substance in the chemical solution at a plurality of preset time points. The method also includes removing the semiconductor wafer from the chemical solution, when the concentration of the substance is maintained at a fixed approximate value.

Abstract: A light emitting diode comprises a light emitting diode chip and a packaging layer. The light emitting diode chip comprises a N-semiconductor layer, a light active layer, and a P-semiconductor layer arranged from a bottom to a top in that sequence, a first electrode, and a second electrode. The first electrode is formed on the P-semiconductor layer. The second electrode is formed on the N-semiconductor layer. The packaging layer covers the light emitting diode chip, and exposes the N-semiconductor layer, the first electrode, and the second electrode. The packaging layer has a through hole separated from a periphery of the light emitting diode chip. A conductive substrate fills the through hole. A first conductive layer is electrically connected to the first electrode and the conductive substrate. The disclosure also provides a method for manufacturing a light emitting diode.

Abstract: A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical solution. The method further includes detecting the concentration of at least one substance in the chemical solution at a plurality of preset time points. The method also includes removing the semiconductor wafer from the chemical solution, when the concentration of the substance is maintained at a fixed approximate value.

Abstract: An illumination device power control module is capable of dynamically adjusting power consumption of a light-emitting diode (LED) illumination device by adjusting the output voltage to different levels to control the power of the light emitting diode illumination device. An alternating current power source terminal is configured to receive an alternating current voltage. A rectifier is configured to convert the alternating current voltage to a rectified voltage.

Abstract: An illumination device power control module is capable of dynamically adjusting power consumption of a light-emitting diode (LED) illumination device by adjusting the output voltage to different levels to control the power of the light emitting diode illumination device. An alternating current power source terminal is configured to receive an alternating current voltage. A rectifier is configured to convert the alternating current voltage to a rectified voltage.

Abstract: This specification provides a burst synchronization and error detection device, which can generate in the synchronization module of the burst synchronization and error detection device a syndrome shared with the error detection module so as to decrease the computation time of the syndrome, shortening the processing time of error detection. The present invention also provides a burst synchronization and error detection method.

Abstract: This specification provides a burst synchronization and error detection device, which can generate in the synchronization module of the burst synchronization and error detection device a syndrome shared with the error detection module so as to decrease the computation time of the syndrome, shortening the processing time of error detection. The present invention also provides a burst synchronization and error detection method.