Patents by Inventor Shih-Chun Fu
Shih-Chun Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420452Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan, Wan-Lin Tsai, Chung-Liang Cheng
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Publication number: 20230317714Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan
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Publication number: 20230290688Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan
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Patent number: 6483751Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: April 24, 2001Date of Patent: November 19, 2002Assignee: Amic TechnologyInventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Publication number: 20020031012Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: ApplicationFiled: April 24, 2001Publication date: March 14, 2002Inventors: Kou-Su Chen, Shih-Chun Fu, Juo-Te Chan
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Patent number: 6353556Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: April 24, 2001Date of Patent: March 5, 2002Assignee: AMIC Technology, Inc.Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Publication number: 20010015911Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: ApplicationFiled: April 24, 2001Publication date: August 23, 2001Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Patent number: 6249459Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: June 21, 2000Date of Patent: June 19, 2001Assignee: AMIC Technology, Inc.Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Patent number: 6219281Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: June 21, 2000Date of Patent: April 17, 2001Assignee: AMIC Technology, Inc.Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Patent number: 6198662Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: June 24, 1999Date of Patent: March 6, 2001Assignee: AMIC Technology, Inc.Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
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Patent number: 6166962Abstract: A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.Type: GrantFiled: June 24, 1999Date of Patent: December 26, 2000Assignee: AMIC Technology, Inc.Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan