Patents by Inventor Shih-Chun Huang

Shih-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840792
    Abstract: An electromagnetic driving mechanism is provided, including a housing, a circuit unit, an electromagnetic driving assembly, and a sensing element. The circuit unit is connected to the housing, and has a plastic material and a circuit element. The plastic material is formed on and covers an outer surface of the circuit element by insert molding. The electromagnetic driving assembly is disposed in the housing for forcing an optical element to move relative to the circuit unit. The sensing element is disposed on the circuit unit, and electrically connected to the circuit element for detecting the displacement of the optical element relative to the circuit unit.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 17, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Kuo-Chun Kao, Nai-Wen Hsu, Shih-Ting Huang, Yi-Hsin Nieh, Meng-Ting Lin
  • Publication number: 20200350311
    Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
    Type: Application
    Filed: July 8, 2020
    Publication date: November 5, 2020
    Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
  • Publication number: 20200333556
    Abstract: A moving-coil closed-loop auto-focusing module with low magnetic interference includes an upper cover, a base frame, a lens module, an elastic module, at least one coil, at least one pair of two opposing driving magnets, an external circuit and at least one sensor magnet. The coil surrounds the lens module. The two driving magnets are located individually at respective lateral sides of the base frame in correspondence with the coil. The external circuit located under the base frame includes an image-sensing element and at least one sensor. The sensor magnet is mounted peripherally to the lens module, and has magnetic lines parallel to the optical image-capturing axis, such that a magnetizing surface of the sensor magnet can face downward to align the sensor on the external circuit. Thereupon, the lens module can be controlled to displace along an optical image-capturing axis in a closed-loop manner.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Applicant: PowerGate Optical Inc.
    Inventors: Ying Chun Huang, Yu Chia Chen, Hsieh Jen Chuang, Te Pao Ho, Shih Chan Wen
  • Publication number: 20200335340
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Patent number: 10804155
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Patent number: 10795102
    Abstract: A interconnection system includes a panel side kit and a wall-mount kit coupled with each other and secured together via magnetic forces. The wall-mount kit includes a printed circuit board enclosed within a bracket and defining a center region for power transmission and a pair of side regions for high speed transmission. In the side regions, on the coupling side a plurality of wireless transmission units are located while on the back side a plurality of ROSA OE modules are provided to transfer the optical signal from optical fibers to the electronic signal for wireless transmission wherein the optical fibers are linked to a control box via a plurality of TOSA EO modules. The panel side kit includes wireless receiving units that interact with the wireless transmission units, and a plurality of connectors with the body of the display.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 6, 2020
    Assignees: FUDING PRECISION COMPONENTS (SHENZHEN) CO., LTD, FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Shih-Wei Hsiao, Hsiu-Yuan Hsu, Wei-Chih Lin, Shuo-Hsiu Hsu, Yen-Hsu Ko, Chih-Chung Hsieh, Cheng-Kai Huang, Paul Chen, Genn-Sheng Lee, Jia-Hau Liu, Mao-Chun Weng, Wayne Chou
  • Publication number: 20200312817
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10790194
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200303351
    Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Publication number: 20200289425
    Abstract: Disclosed herein are drug-containing vesicles, each of which includes a carbon dot liposome (C-dot liposome) formed by a plurality of Janus particles, which are self-assembled into the C-dot liposome; and a drug encapsulated within the C-dot liposome. Also disclosed herein is a method of producing the drug-containing vesicles. The method includes, mixing a plurality of Janus particles with a drug solution (e.g., an anti-cancer drug solution) to form a mixed solution; and producing the drug-containing vesicles either by a film-hydration method or an injection method. In the film-hydration method, the mixed solution is condensed until a film-like structure is formed; and sonicating the film-like structure in a salt solution to produce the drug-containing vesicle. In the injection method, the mixed solution is rapidly injected into a salt solution to produce the drug-containing vesicle. Also encompasses in the present disclosure are methods for treating a subject afflicted with a cancer.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: National Taiwan University
    Inventors: Huan-Tsung CHANG, Yu-Feng LIN, Shih-Chun WEI, Yu-Ting TSENG, Yu-Feng HUANG, Chih-Ching HUANG, Yu-Syuan LIN, Tzu-Heng CHEN
  • Patent number: 10764475
    Abstract: A driving mechanism is provided, including a housing, a hollow frame, a holder, and a driving assembly. The frame is fixed to the housing and has a stop surface. The holder is movably disposed in the housing for holding the optical element. The driving assembly is disposed in the housing to drive the holder and the optical element moving along the optical axis of the optical element relative to the frame. Specifically, the stop surface is parallel to the optical axis to contact the holder and restrict the holder in a limit position.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 10756121
    Abstract: A conductor structure includes a first metal layer, a second metal layer, and a controlling layer. The second metal layer is disposed on the first metal layer. A material of the first metal layer and a material of the second metal layer include at least one identical metal element. The controlling layer is disposed between the first metal layer and the second metal layer. A thickness of the controlling layer is less than a thickness of the first metal layer, and the thickness of the controlling layer is less than a thickness of the second metal layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 25, 2020
    Assignee: Innolux Corporation
    Inventors: Ming-Chun Chen, Hsu-Min Huang, Shih-Sian Yang
  • Patent number: 10756086
    Abstract: A method of manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. The second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
  • Publication number: 20200266271
    Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20200243971
    Abstract: A millimeter wave antenna device includes an antenna array, a first parasitic element and a second parasitic element. The antenna array includes m×n antennas and is disposed in an antenna area. The first parasitic element is disposed beside a first side of the antenna area. The second parasitic element is disposed beside a second side of the antenna area. None of the first parasitic element and the second parasitic element overlaps with the antenna area.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 30, 2020
    Inventors: Shao-Yu Huang, Yeh-Chun Kao, Chung-Hsin Chiang, Shih-Huang Yeh
  • Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10725266
    Abstract: A moving-coil closed-loop auto-focusing module with low magnetic interference includes an upper cover, a base frame, a lens module, an elastic module, at least one coil, at least one pair of two opposing driving magnets, an external circuit and at least one sensor magnet. The coil surrounds the lens module. The two driving magnets are located individually at respective lateral sides of the base frame in correspondence with the coil. The external circuit located under the base frame includes an image-sensing element and at least one sensor. The sensor magnet is mounted peripherally to the lens module, and has magnetic lines parallel to the optical image-capturing axis, such that a magnetizing surface of the sensor magnet can face downward to align the sensor on the external circuit. Thereupon, the lens module can be controlled to displace along an optical image-capturing axis in a closed-loop manner.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 28, 2020
    Assignee: PowerGate Optical Inc.
    Inventors: Ying Chun Huang, Yu Chia Chen, Hsieh Jen Chuang, Te Pao Ho, Shih Chan Wen
  • Patent number: 10725212
    Abstract: A lens includes a curved surface. A plurality of taper shape structures is formed on the curved surface, and each taper shape structure has at least three substantial flat surfaces. P is less than or equal to 500 nm. H is less than or equal to 500 nm. The P refers to the pitch between two adjacent taper shape structures. The H refers to maximum vertical distance between each taper shape structure and the curved surface.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Young Optics Inc.
    Inventors: Shih-Chang Liu, Chih-Chun Huang, Kai-Wei Hu
  • Publication number: 20200235214
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Patent number: D891504
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao