Patents by Inventor Shih-Chun Tsai

Shih-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079237
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 12183626
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 31, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Publication number: 20220384254
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 11450558
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Publication number: 20200373198
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 10784153
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Publication number: 20200058544
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Application
    Filed: September 18, 2018
    Publication date: February 20, 2020
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 9316901
    Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
  • Publication number: 20140220482
    Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 7, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
  • Patent number: 8748066
    Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: June 10, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
  • Patent number: 8735295
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
  • Publication number: 20140093814
    Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 3, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
  • Publication number: 20130337650
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai