Patents by Inventor Shih-Chun Tsai
Shih-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250079237Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.Type: ApplicationFiled: November 18, 2024Publication date: March 6, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Patent number: 12183626Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.Type: GrantFiled: August 9, 2022Date of Patent: December 31, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Publication number: 20220384254Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Patent number: 11450558Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.Type: GrantFiled: August 12, 2020Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Publication number: 20200373198Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Patent number: 10784153Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.Type: GrantFiled: September 18, 2018Date of Patent: September 22, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Publication number: 20200058544Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.Type: ApplicationFiled: September 18, 2018Publication date: February 20, 2020Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
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Patent number: 9316901Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.Type: GrantFiled: April 23, 2014Date of Patent: April 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
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Publication number: 20140220482Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.Type: ApplicationFiled: April 23, 2014Publication date: August 7, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
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Patent number: 8748066Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.Type: GrantFiled: October 3, 2012Date of Patent: June 10, 2014Assignee: United Microelectronics Corp.Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
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Patent number: 8735295Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.Type: GrantFiled: June 19, 2012Date of Patent: May 27, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
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Publication number: 20140093814Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.Type: ApplicationFiled: October 3, 2012Publication date: April 3, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chia-Wei Huang, Chun-Hsien Huang, Shih-Chun Tsai, Kai-Lin Chuang
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Publication number: 20130337650Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.Type: ApplicationFiled: June 19, 2012Publication date: December 19, 2013Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai