Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.

Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.

Abstract: A communication device and a method of processing input data. The communication device, processing input data constituting at least one of data packet comprises a detection unit, an Automatic Gain Controller (AGC), a signal processor, a demodulator, a pre-detection module, and a Baseband module. The detection unit receives the input data to perform the packet detection. The Automatic Gain Controller, coupled to the detection unit, generates an adjusted data and a gain control parameter once packet is detected. The signal processor, coupled to the AGC, performs the data signal processing includes at least one of analog to digital transformation processing, radio frequency processing and baseband processing, and detects at least one of the desired signal, noise and interference. The demodulator, coupled to the signal processor, demodulates the processed data into a processed data according to at least one processing function of noise reduction, interference reduction, and signal compensation.

Abstract: An apparatus for survivor path decoding in a Viterbi decoder with a constraint length of K. The apparatus of the invention includes a best survivor unit, a a register-exchange network, and a trace-back unit. The best survivor unit receives path metrics of 2K?2 local winner states from which a best state is selected every L iterations. Meanwhile, the register-exchange network generates decision vectors of survivor paths leading to 2K?1 states at instant i according to decision bits of all states from instant i?L to instant i. Every L iterations the register-exchange network outputs L-bit decision vectors for all states at instant i. Then the trace-back unit stores the decision vectors and finds a global survivor path sequence by following the decision vectors back from the best state at instant i?L. In this manner, L decoded bits can be output from the trace-back unit every L iterations.

Abstract: A communication device and a method of processing input data. The communication device, processing input data constituting at least one of data packet comprises a detection unit, an Automatic Gain Controller (AGC), a signal processor, a demodulator, a pre-detection module, and a Baseband module. The detection unit receives the input data to perform the packet detection. The Automatic Gain Controller, coupled to the detection unit, generates an adjusted data and a gain control parameter once packet is detected. The signal processor, coupled to the AGC, performs the data signal processing includes at least one of analog to digital transformation processing, radio frequency processing and baseband processing, and detects at least one of the desired signal, noise and interference. The demodulator, coupled to the signal processor, demodulates the processed data into a processed data according to at least one processing function of noise reduction, interference reduction, and signal compensation.

Abstract: A method, algorithm, architecture, circuits, and/or systems for robust radar signal detection for wireless communications are disclosed. In one embodiment, a method of detecting a predefined signal pulse event in a wireless network device can include the steps of: (i) comparing a power of a received signal pulse to a predetermined power threshold of a predefined signal; (ii) determining a duration of the received signal pulse when the power of the received signal pulse is greater than the predetermined power threshold; and (iii) indicating an occurrence of the predetermined signal pulse event when the duration of the received signal pulse is between first and second predetermined duration thresholds of the predefined signal. The predefined signal pulse event can be a radar signal pulse, for example. Embodiments of the present invention can advantageously provide a reliable and simplified approach for radar signal detection suitable for wireless network devices.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: A de-interleaver for data decoding. Two memory banks are configured to store data in column order and output the data in row order. A de-interleaving encoder receives a stream of interleaved data values, generates an input address for both the two memory banks contingent upon a modulation mode and based on a count value, and sequentially writes the interleaved data values to either of the memory banks according to the input address. Additionally, a de-interleaving decoder generates respective output addresses for the two memory banks based on a second count value and contingent upon the modulation mode, and a dummy insertion indicator. The de-interleaving decoder reads the interleaved data values from the two memory banks according to the respective output address, and extracts decision metrics from the read data according to relevant output indicators.

Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX) The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.

Abstract: An apparatus for branch metric computation and add-compare-select operation in a rate 1/n Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a measure between a currently received data symbol and a corresponding branch label. The add-compare-select unit can generate respective decision bits for a pair of odd and even states at next instant with a novel pre-computational architecture. Further, a local winner between the odd and even states is predetermined in a manner providing reduction of the activity required by the computation. Thus the add-compare-select unit outputs a path metric of the local winner, whereby a saving of half the output number of path metrics is achieved.

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: An apparatus for branch metric computation and add-compare-select operation in a rate 1/n Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a measure between a currently received data symbol and a corresponding branch label. The add-compare-select unit can generate respective decision bits for a pair of odd and even states at next instant with a novel pre-computational architecture. Further, a local winner between the odd and even states is predetermined in a manner providing reduction of the activity required by the computation. Thus the add-compare-select unit outputs a path metric of the local winner, whereby a saving of half the output number of path metrics is achieved.

Abstract: A receiver in a home phone-lines local area network system is proposed. The receiver can distinguish a valid signal and a collision backoff signal from noises in real time. The receiver for a home phone-lines LAN system comprises a QAM demodulator, an equalizer, a deconstellation, and a transmission data reading device. The receiver further comprises a signal match filter module and a detector. The signal match filter module comprises an adder and at least a cross-correlator. The adder adds the “I” signal and “Q” signal outputted from the QAM demodulator and outputs a combined signal. The cross-correlator performs match operation, such as a comparison operation or a correlation operation, of the combined signal and an identification value and outputs a match value to the detector. Since the signal match filter module connects directly to the output of QAM demodulator, it can immediately identify the identification code TRN16 contained in the received signal.

Abstract: A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.