Abstract: An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.

Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.

Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.