Patents by Inventor Shih-Feng Su

Shih-Feng Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Patent number: 8431473
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • Publication number: 20130009288
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • Patent number: 7763522
    Abstract: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: July 27, 2010
    Assignee: United Microelectronic Corp.
    Inventor: Shih-Feng Su
  • Publication number: 20090035915
    Abstract: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 5, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Shih-Feng Su
  • Publication number: 20080026579
    Abstract: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the copper damascene process are removed by the heat treatment, therefore the copper damascene structure is completely reduced by the reduction plasma treatment and is improved.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Inventors: Kuo-Chih Lai, Mei-Ling Chen, Jei-Ming Chen, Hsin-Hsing Chen, Shih-Feng Su, Meng-Chi Chen