Patents by Inventor Shih-Feng Wu

Shih-Feng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12137569
    Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Yu-Ming Lin, Shih-Lien Linus Lu, Sai-Hooi Yeong, Bo-Feng Young
  • Publication number: 20240355628
    Abstract: A wafer processing method including following steps is provided. A release layer is formed on a first wafer. An adhesive layer is formed on a second wafer. One of the first wafer and the second wafer is a device wafer. The device wafer includes a valid die region and a trimming region. A handler is applied to place the first wafer on the second wafer, so that the release layer and the adhesive layer are bonded to each other, and the adhesive layer completely covers the valid die region. During the process of placing the first wafer on the second wafer, the handler directly moves the first wafer.
    Type: Application
    Filed: May 23, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Fu Wu, Shih-Ping Lee, Yu-Chun Huo, Chih Feng Sung, Ming-Jui Tsai
  • Publication number: 20240355784
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Publication number: 20240297138
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first substrate and through vias formed through the first substrate. The package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. The package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. The package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 12040235
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20220080441
    Abstract: The present invention discloses a shielding jig which mainly comprises an adjustment unit, a positioning unit and a sealing unit. The adjustment unit is configured and engaged between the positioning unit and the sealing unit. Therefore, a first actuation surface of the adjustment unit matches with a second actuation surface of the sealing unit, resulting in expansion of the sealing unit. This expansion makes the shielding jig be able to shade and seal any workpiece.
    Type: Application
    Filed: January 31, 2021
    Publication date: March 17, 2022
    Inventors: MING-CHIEN CHIU, EN-NIEN SHEN, YUNG-CHIN PAN, SHIH-FENG WU
  • Publication number: 20100319119
    Abstract: A movable sink is provided with a body which is connected with a discharge element. The movable sink also includes at least one sink and one moving device, and the sink is located inside the body and is provided with an inlet and an outlet. The outlet is connected to the discharge element, and the moving device is located at a bottom of the body. After a water supply has been replenished from the inlet, the movable sink can be moved to any place to provide the water supply by the moving device.
    Type: Application
    Filed: February 7, 2008
    Publication date: December 23, 2010
    Inventor: Shih-Feng Wu