Patents by Inventor Shih-Han Kao

Shih-Han Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154025
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11942363
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 11923440
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Patent number: 8975234
    Abstract: A method of inhibiting the growth of Gram-positive bacteria comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is provided. The Gram-positive bacteria comprise methicillin-resistant Staphylococcus aureus. A method of treating sepsis comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is also provided. A method of treating leukemia comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is further provided.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 10, 2015
    Assignee: Kaohsiung Medical University
    Inventors: Lih-Geeng Chen, Yen-Hsu Chen, Chin Hsu, Hsin-Ju Chien, Shih-Han Kao, Yu-Wei Chang, Wan-Chun Huang
  • Publication number: 20120190632
    Abstract: A method of inhibiting the growth of Gram-positive bacteria comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is provided. The Gram-positive bacteria comprise methicillin-resistant Staphylococcus aureus. A method of treating sepsis comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is also provided. A method of treating leukemia comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is further provided.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Lih-Geeng Chen, Yen-Hsu Chen, Chin Hsu, Hsin-Ju Chien, Shih-Han Kao, Yu-Wei Chang, Wan-Chun Huang