Patents by Inventor Shih-Hang Chiu
Shih-Hang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961732Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.Type: GrantFiled: July 25, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee
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Publication number: 20240096883Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
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Publication number: 20240097005Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hang Chiu, Jui-Yang Wu, Kuan-Ting Liu, Weng Chang
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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GATE STRUCTURE, FIN FIELD-EFFECT TRANSISTOR, AND METHOD OF MANUFACTURING FIN-FIELD EFFECT TRANSISTOR
Publication number: 20240088144Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu -
Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
Patent number: 11855083Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure.Type: GrantFiled: February 8, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu -
Publication number: 20230386926Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: ApplicationFiled: August 2, 2023Publication date: November 30, 2023Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Publication number: 20230343857Abstract: In a method of manufacturing a semiconductor device, a lower conductive layer is formed in an opening formed in a dielectric layer, and the lower conductive layer is recessed to form a space. A blanket conductive layer is formed over the recessed lower conductive layer in the space, a sidewall of the space and an upper surface of the dielectric layer. Part of the blanket conductive layer formed on the sidewall of the opening and the upper surface of the dielectric layer is removed, thereby forming a upper conductive layer on the lower conductive layer, and a cap insulating layer is formed over the upper conductive layer in the space. The blanket conductive layer is formed by physical vapor deposition.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: An-Hung TAI, Chia-Wei CHEN, Shih-Hang CHIU, Yu-Hong LU, Hui-Chi CHEN, Kuo-Feng YU, Jian-Hao CHEN
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Publication number: 20230317799Abstract: A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.Type: ApplicationFiled: May 23, 2022Publication date: October 5, 2023Inventors: Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Patent number: 11728341Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: GrantFiled: March 24, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20230223253Abstract: In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.Type: ApplicationFiled: May 17, 2022Publication date: July 13, 2023Inventors: Shih-Hang CHIU, Chi On CHUI
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Publication number: 20230215929Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen
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Publication number: 20230155002Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.Type: ApplicationFiled: March 22, 2022Publication date: May 18, 2023Inventors: Shih-Hang Chiu, Wei-Cheng Wang, Chung-Chiang Wu, Chi On Chui
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Publication number: 20230140968Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: ApplicationFiled: January 13, 2023Publication date: May 11, 2023Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Patent number: 11605720Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.Type: GrantFiled: February 26, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen
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Patent number: 11594610Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: GrantFiled: February 2, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Publication number: 20230028460Abstract: A semiconductor device includes an active region. A metal gate electrode is disposed over the active region. A conductive layer is disposed over the metal gate electrode. A silicon-containing layer is disposed over a first portion of the conductive layer. A dielectric layer is disposed over a second portion of the conductive layer. A gate via vertically extends through the silicon-containing layer. The gate via is disposed over, and electrically coupled to, the metal gate electrode.Type: ApplicationFiled: April 21, 2022Publication date: January 26, 2023Inventors: Wei-Cheng Wang, Shih-Hang Chiu, Kuan-Ting Liu, Cheng-Lung Hung, Chi On Chui
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Publication number: 20230016381Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.Type: ApplicationFiled: May 6, 2022Publication date: January 19, 2023Inventors: Wei-Cheng Wang, Shih-Hang Chiu, Kuan-Ting Liu, Chi On Chui, Chia-Wei Chen, Jian-Hao Chen
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Publication number: 20230010952Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.Type: ApplicationFiled: May 5, 2022Publication date: January 12, 2023Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen, Chun-Chih Cheng
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Publication number: 20230010065Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.Type: ApplicationFiled: June 7, 2022Publication date: January 12, 2023Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui