Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A multiple inlets cyclo-filtration hydrocyclone separator includes a separator body having an upper body part and a lower body part narrower than the upper body part in diameter; at least two feeders connected helically to the upper body part from a lateral side for feeding in a raw liquid; an upstream outlet disposed axially within the separator body, having an upper part projecting upward and axially from the upper body part and a lower part extending into the lower body part; a downstream outlet attached axially to the lower body part in spatially communication therewith; and a filtering unit disposed axially within an inner wall confining the upstream outlet. The filtering unit has an upper part projecting upwardly and outwardly from a top end of the upstream outlet and a lower part extending into the downstream outlet. The filtering unit consists of a filtering membrane having an inner wall confining the filtering member.

Abstract: An electronic device is provided, which may include a biometric module, a processing module and a light transmission module. The biometric module may recognize a biological feature, and convert the biological feature into a biological feature signal via an analysis algorithm. The processing module may encrypt an international mobile equipment identity number of the electronic device and the biological feature signal to generate an encrypted signal, and convert the encrypted signal into a visible light signal. The light transmission module may transmit the visible light signal to a controlled device.

Abstract: An indoor air quality control system, including a plurality of fixed detectors, an unmanned vehicle platform and a cloud computing platform. The fixed detectors detect the indoor air quality at respective designated positions in an indoor area. The unmanned vehicle platform moves along a designated route in the indoor area. When an index corresponding to the indoor air quality at a designated position reaches an air pollution warning value, a processing unit of the unmanned vehicle platform controls the unmanned vehicle platform to move towards a corresponding one of the designated positions and controls an air cleaning device on the unmanned vehicle platform to perform air cleaning. The cloud computing platform receives the indoor air quality detected by the respective fixed detectors and the mobile air quality detected by a mobile detector on the unmanned vehicle platform over the Internet.

Abstract: An indoor air quality control system, including a plurality of fixed detectors, an unmanned vehicle platform and a cloud computing platform. The fixed detectors detect the indoor air quality at respective designated positions in an indoor area. The unmanned vehicle platform moves along a designated route in the indoor area. When an index corresponding to the indoor air quality at a designated position reaches an air pollution warning value, a processing unit of the unmanned vehicle platform controls the unmanned vehicle platform to move towards a corresponding one of the designated positions and controls an air cleaning device on the unmanned vehicle platform to perform air cleaning. The cloud computing platform receives the indoor air quality detected by the respective fixed detectors and the mobile air quality detected by a mobile detector on the unmanned vehicle platform over the Internet.

Abstract: An electronic device is provided, which may include a biometric module, a processing module and a light transmission module. The biometric module may recognize a biological feature, and convert the biological feature into a biological feature signal via an analysis algorithm. The processing module may encrypt an international mobile equipment identity number of the electronic device and the biological feature signal to generate an encrypted signal, and convert the encrypted signal into a visible light signal. The light transmission module may transmit the visible light signal to a controlled device.

Abstract: A method and system of merging one-bit cells in an integrated circuit layout, comprising a database to store the layout, a placer in communication with the database to update the layout, and a merger in communication with the placer. The merger is configured to: identify a set of one-bit cells in the integrated circuit layout; determine a set of merge cells, from among the identified set of one-bit cells, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and generate instructions to the placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

Abstract: A voltage detector to detect the voltage level of a switched power supply associated with a power gated region of an integrated circuit. The voltage detection circuit, which can be described as a modified Schmitt trigger circuit, comprises PMOS and NMOS transistors, and an added stack of NMOS transistors to set the output to a value of 1 in response to detection of an input voltage at the input greater than an operational voltage of the switched power supply, for example approximately 80% VDD and above. A pull-down circuit actively pulls the circuit output low before the circuit input drops below the low input threshold. Optional additional NMOS transistors provide the capability to adjust the threshold. The voltage detector circuit can be calibrated and used to detect whether or not the switched power supply associated with a power gated design has reached its operational voltage level.

Abstract: The present disclosure provides a monitoring system for monitoring the operation of an integrated circuit, the monitoring system comprising: a reference circuit comprising a reference signal delay path and an output for outputting a reference signal; a monitoring circuit, the monitoring circuit comprising: a programmable delay line for providing a controllably selectable delay path; and an output for outputting a delayed signal; a comparison circuit, for comparing the reference signal to the delayed signal and determining whether the error has occurred based on the comparison.

Abstract: A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.