Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The active region is located between the first semiconductor structure and the second semiconductor structure. The active region includes a light-emitting region having N pair(s) of semiconductor stack(s). Each of the semiconductor stack includes a well layer and a barrier layer, in which N is a positive integer greater than or equal to 1. The well layer includes a first group III-V semiconductor material including indium with a first percentage of indium content. The barrier layer includes a second group III-V semiconductor material including indium with a second percentage of indium content. The first group III-V semiconductor material and the second group III-V semiconductor material further includes phosphorus. The second percentage of indium content is less than the first percentage of indium content.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: A method for forming a package structure is provided, wherein the method includes forming an interconnect structure in a substrate. The method also includes bonding a chip over the substrate and electrically connected to the interconnect structure. The method includes bonding a plurality of dies over the substrate and adjacent to the chip. The method also includes supplying a molding material to the gap between the chip and the dies, after which the method includes thinning down the substrate.

Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: An electronic device and a method of transmitting USB commands are provided. The method includes: (A) allocating a buffer area in a memory; (B) receiving a USB command; (C) retrieving control transfer information of the USB command; (D) storing the control transfer information in the buffer area; (E) repeating steps (B) to (D) until a condition for ending a control aggregation is met; (F) generating an aggregated USB command according to the content of the buffer area; and (G) transmitting the aggregated USB command.

Abstract: A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.

Abstract: A side by side image detection method and an electronic apparatus using the same are provided. The side by side image detection method includes the following steps. A first image with a first image size is obtained. A second image with a second image size that conforms to a side-by-side image format is detected within the first image by using a convolutional neural network model.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: A current detection method adapted to an inverter is provided, which includes: determining that a plurality of lower arms of an inverter have a minimum conduction period when all the lower arms are turned on simultaneously; determining a sampling time point according to the minimum conduction period, wherein a period from a starting point of the minimum conduction period to the sampling time point is defined as a sampling period that is close to the minimum conduction period; simultaneously detecting currents flowing through the lower arms by a plurality of detection resistors to generate a plurality of measurement voltages; and determining the currents of the inverter according to the measurement voltages.

Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: A method of inspecting an outer surface of a mask pod includes moving a stage holding a mask pod such that the stage stops at each location of a plurality of locations under an outer surface of the mask pod for a predefined amount of time. At each location of the plurality of locations, the method further includes directing a stream of air to the outer surface of the mask pod, capturing an image of scattered air from each location of the plurality of locations of the outer surface of the mask pod, and determining a number of particles in the scattered air as a sampled number of particles based on the captured image. The method also includes generating a map of particles on the outer surface of the mask pod based on the sampled number of particles at each of the plurality of locations.

Abstract: A stereo image generation method and an electronic apparatus using the same are provided. The stereo image generation method includes the following steps. A two-dimensional (2D) original image corresponding to a first viewing angle is obtained, and a depth map of the 2D original image is estimated. Interpupillary distance information of a user is detected. A pixel shift processing is performed on the 2D original image according to the interpupillary distance information and the depth map to generate a reference image corresponding to a second viewing angle. An image inpainting processing is performed on the reference image to obtain a restored image. The restored image and the 2D original image are merged to generate a stereo image conforming to a stereo image format.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.

Abstract: A clip pushing structure for a clip applier, which is used to install and push clips. The clip pushing structure comprises: a nail mounting groove piece which has a receiving slot, wherein the clips are placed in the receiving slot of the nail mounting groove piece in a continuous abutting manner; a screw-in ladder member which has a nail-pushing part and a plurality of pushed parts, a pitch being formed between every two pushed parts; a nail pushing member which has a body, a front pushing part that may push the foremost clip, and a rear pushing part that may push each pushed part of the screw-in ladder member; and a clamping jaw which penetrates a clamping jaw assembly, the clamping jaw having two arms which each have a convex part and abut against a left side wall and a right side wall of the clamping jaw assembly.

Abstract: A clip pushing structure for a clip applier, which is used to install and push clips. The clip pushing structure comprises: a nail mounting groove piece which has a receiving slot, wherein the clips are placed in the receiving slot of the nail mounting groove piece in a continuous abutting manner; a screw-in ladder member which has a nail-pushing part and a plurality of pushed parts, a pitch being formed between every two pushed parts; a nail pushing member which has a body, a front pushing part that may push the foremost clip, and a rear pushing part that may push each pushed part of the screw-in ladder member; and a clamping jaw which penetrates a clamping jaw assembly, the clamping jaw having two arms which each have a convex part and abut against a left side wall and a right side wall of the clamping jaw assembly.

Abstract: An operating structure of a surgical clip applier is provided to drive a clip clamping unit. The operating structure of the surgical clip applier comprises: a body; a front driving element for driving the clip clamping unit; a restoring spring for driving the front driving element to move backward; a press-control element pivotally connected to the body; a front driving arm pivotally connected to the press-control element; and a lower driving arm with two ends pivotally connected to the body and the front driving arm, respectively, to drive the front driving element to move forward.