Patents by Inventor Shih-Hao Ou

Shih-Hao Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11839027
    Abstract: An electronic device with a connector structure is provided. The electronic device includes a first circuit board, a first connector, a first shielding cover, a second circuit board, a second connector, and a second shielding cover. The first connector is disposed on the first circuit board. The first shielding cover is disposed on the first circuit board and surrounds the first connector. The second connector is disposed on the second circuit board, wherein the second connector is connected to the first connector. The second shielding cover is disposed on the second circuit board and surrounds the second connector, wherein the first shielding cover is electrically connected to the second shielding cover.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 5, 2023
    Assignee: WISTRON NEWEB CORP.
    Inventors: Yan-Da Chen, Shih-Hao Ou
  • Patent number: 11442220
    Abstract: A light indicator module is provided. The light indicator module includes a circuit board, a plurality of light sources, a light guide unit, and a shielding material. The light sources are disposed on the circuit board, and each light source provides a light beam. The light guide unit includes a plurality of guiding blocks. Each guiding block includes a light emitting surface, a light entering side surface, and at least one abuttal side surface. One of the light sources corresponds to the light entering side surface. The light beam enters the guiding block through the light entering side surface and is emitted through the light emitting surface. The abuttal side surface faces toward an adjacent guiding block. The shielding material covers the abuttal side surface.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 13, 2022
    Assignee: WISTRON NEWEB CORP.
    Inventors: Ying-Yen Lu, Yan-Da Chen, Shih-Hao Ou
  • Publication number: 20220015235
    Abstract: An electronic device with a connector structure is provided. The electronic device includes a first circuit board, a first connector, a first shielding cover, a second circuit board, a second connector, and a second shielding cover. The first connector is disposed on the first circuit board. The first shielding cover is disposed on the first circuit board and surrounds the first connector. The second connector is disposed on the second circuit board, wherein the second connector is connected to the first connector. The second shielding cover is disposed on the second circuit board and surrounds the second connector, wherein the first shielding cover is electrically connected to the second shielding cover.
    Type: Application
    Filed: April 23, 2021
    Publication date: January 13, 2022
    Inventors: Yan-Da CHEN, Shih-Hao OU
  • Patent number: 8972471
    Abstract: An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 3, 2015
    Assignee: National Chiao Tung University
    Inventors: Chih-Wei Liu, Kuo-Chiang Chang, Shih-Hao Ou, Yu-Wen Chen
  • Patent number: 8972699
    Abstract: A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Tai-Ji Lin, Tien-Wei Hsieh, Yuan-Hua Chu, Shih-Hao Ou, Xiang-Sheng Deng, Chih-Wei Liu
  • Publication number: 20130311529
    Abstract: An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor.
    Type: Application
    Filed: September 12, 2012
    Publication date: November 21, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chih-Wei Liu, Kuo-Chiang Chang, Shih-Hao Ou, Yu-Wen Chen
  • Publication number: 20090172683
    Abstract: A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.
    Type: Application
    Filed: April 22, 2008
    Publication date: July 2, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tai-Ji Lin, Tien-Wei Hsieh, Yuan-Hua Chu, Shih-Hao Ou, Xiang-Sheng Deng, Chih-Wei Liu