Patents by Inventor Shih-Hao Wu
Shih-Hao Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12237262Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.Type: GrantFiled: November 6, 2023Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
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Patent number: 12235586Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.Type: GrantFiled: August 7, 2023Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hao Lai, Ming-Hsun Tsai, Hsin-Feng Chen, Wei-Shin Cheng, Yu-Kuang Sun, Cheng-Hsuan Wu, Yu-Fa Lo, Shih-Yu Tu, Jou-Hsuan Lu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20250063789Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.Type: ApplicationFiled: August 15, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Hsiang SU, Ping-Chun WU, Je-Wei HSU, Hong-Chih CHEN, Chia-Hao KUO, Shih-Hsun CHANG
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Patent number: 12231201Abstract: A reconfiguration intelligent surface device and a beamforming method thereof, the beamforming method adapted to the reconfiguration intelligent surface device is described below. A timing synchronization signal is received. A frame boundary synchronized with a radio signal transmission/reflection device is established according to the timing synchronization signal. Beam control information is received. A reflected beam is formed by reflecting a radio signal beam transmitted or reflected by the radio signal transmission/reflection device according to the beam control information based on the frame boundary synchronized with the radio signal transmission/reflection device.Type: GrantFiled: December 23, 2022Date of Patent: February 18, 2025Assignee: Industrial Technology Research InstituteInventors: Chiu-Ping Wu, Shih-Hao Fang, Hsin-An Hou, Jen-Yuan Hsu
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Patent number: 12230507Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.Type: GrantFiled: April 25, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
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Publication number: 20250048706Abstract: A sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. The sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. The sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. The sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. Thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.Type: ApplicationFiled: November 2, 2023Publication date: February 6, 2025Inventors: Tsung-Jui WU, Tsung-Yin HSU, Ying Ming WANG, Shih-Hao CHEN, Sung-Hsin YANG
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Publication number: 20250048493Abstract: Techniques pertaining to power saving by data throughput pattern prediction in wireless communications are described. A user equipment (UE) determines whether a probability of a first value being greater than a second value is higher than a threshold. The UE triggers a radio resource control (RRC) connection release with a network responsive to the probability being higher than the threshold. The first value represents a succeeding continuous duration of no uplink (UL) and downlink (DL) data. The second value represents an RRC inactivity timer duration plus a threshold duration.Type: ApplicationFiled: August 4, 2023Publication date: February 6, 2025Inventors: Hung-Yueh Chen, Byeng Hyun Kim, Jung Shup Shin, Pei-Tsung Wu, Wei-Hao Pan, Shih-Wei Sun, Wei-Ming Yin
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Publication number: 20250029949Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.Type: ApplicationFiled: November 1, 2023Publication date: January 23, 2025Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chih-Feng Sung, Chih-Hao Chuang, Chun-Lin Lu, Shih-Ping Lee, Li-Han Chiu, Yi-Kai Wu
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Patent number: 9008098Abstract: A network communication system comprises a cloud network and at least one physical machine. The cloud network comprises at least one physical switch. Each the physical machine comprises a plurality of virtual machines and a virtual switch. Each of the virtual machines is connected to the at least one physical switch in the cloud network through the virtual switch. The virtual switch encapsulates a destination machine address of an egress frame sent by the virtual machines, attaches a destination switch address to the egress frame to be forwarded to the at least one physical switch, and receives and analyzes an ingress frame obtained from the at least one physical switch, so as to convert the destination switch address of the ingress frame to the destination machine address, for forwarding the ingress frame to one of the virtual machines.Type: GrantFiled: March 13, 2013Date of Patent: April 14, 2015Assignees: Inventec (Pudong) Technology Corporation, Inventec CorporationInventors: Jenn-Huei Tseng, Shih-Hao Wu, Yi-Kuan Wu, Te-Yen Liu
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Publication number: 20140119375Abstract: A network communication system comprises a cloud network and at least one physical machine. The cloud network comprises at least one physical switch. Each the physical machine comprises a plurality of virtual machines and a virtual switch. Each of the virtual machines is connected to the at least one physical switch in the cloud network through the virtual switch. The virtual switch encapsulates a destination machine address of an egress frame sent by the virtual machines, attaches a destination switch address to the egress frame to be forwarded to the at least one physical switch, and receives and analyzes an ingress frame obtained from the at least one physical switch, so as to convert the destination switch address of the ingress frame to the destination machine address, for forwarding the ingress frame to one of the virtual machines.Type: ApplicationFiled: March 13, 2013Publication date: May 1, 2014Applicants: INVENTEC CORPORATION, INVENTEC (PUDONG) TECHNOLOGY CORPORATIONInventors: Jenn-Huei Tseng, Shih-Hao Wu, Yi-Kuan Wu, Te-Yen Liu
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Patent number: 8673788Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.Type: GrantFiled: July 28, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsiu Cheng, Shih-Hao Wu, Chih-Hsien Hsu, Chia-Chi Chung, Wei-Yueh Tseng
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Publication number: 20120028468Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.Type: ApplicationFiled: July 28, 2010Publication date: February 2, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hsiu Cheng, Shih-Hao Wu, Chih-Hsien Hsu, Chia-Chi Chung, Wei-Yueh Tseng