Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A method used for object tracking includes: using a specific object model to generate a first vector of a first ratio object and a second vector of a second ratio object of an image in an object detection bounding box of a specific frame; generating an identity label of an object within the bounding box according to the first vector, the second vector, and M first ratio reference vectors and M second ratio reference vectors stored in an object vector database.

Abstract: A method of performing person re-identification includes: obtaining a person feature vector according to an extracted image containing a person; obtaining state information of the person according to a state of the person in the extracted image; comparing the person feature vector with a plurality of registered person feature vectors in a database; when the person feature vector successfully matches a first registered person feature vector of the plurality of registered person feature vectors, identifying the person as a first identity corresponding to the first registered person feature vector; and selectively utilizing the person feature vector to update one of the first registered person feature vector and at least one second registered person feature vector that correspond to the first identity according to the state information.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. The conductive contact is disposed in the second interlayer dielectric layer.

Abstract: A method of fabricating a semiconductor device includes forming, over a substrate, alternating layers of a first semiconductor layer formed of a first semiconductor material and a second semiconductor layer formed of a second semiconductor material, the first semiconductor layers including a first, a second, and a third sub-layers; patterning the alternating layers of the first and the second semiconductor layers to form stacks of the alternating layers; and exposing, under etch conditions, lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure on a semiconductor substrate. A gate electrode structure is on the gate dielectric structure. The gate electrode structure includes a lower conductive structure and a gate body structure. The gate body structure includes an upper segment over a top surface of the lower conductive structure and a lower segment disposed between opposing inner sidewalls of the lower conductive structure.

Abstract: A training system, a training method, and a recognition system are provided. The training method is used to train a neural network module including: an encoder module, a shared decoder module, a synthesis module, and a classification module. The training method includes performing in a training epoch: repeatedly executing: taking a training image from a training set as an input image, obtaining a first loss based on training feature images of the training image and the feature images corresponding to the training image, and obtaining a second loss based on a classification marker of the training image and a classification generated by the classification module in correspondence with the training image; and updating first parameters and second parameters based on an average value of all the first losses and an average value of all the second losses obtained in the preceding step and an update algorithm.

Abstract: A neural network system and a signal processing method are provided. The neural network system includes at least one processing unit and a neural network module. The signal processing method includes: inputting a neural network input to the neural network module by the processing unit to generate an input at a previous layer of each convolutional transformer layer; performing pointwise convolution on the input by a key embedding layer based on key convolutional kernels to output a key tensor; performing convolution on the input by a value embedding layer based on value convolutional kernels to output a value tensor; performing a convolution on the cascading tensor of a first tensor and the key tensor by an attention embedding layer based on attention convolution kernels to output an attention tensor; and outputting an output tensor based on the attention tensor and the value tensor by an output module.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A network communication system comprises a cloud network and at least one physical machine. The cloud network comprises at least one physical switch. Each the physical machine comprises a plurality of virtual machines and a virtual switch. Each of the virtual machines is connected to the at least one physical switch in the cloud network through the virtual switch. The virtual switch encapsulates a destination machine address of an egress frame sent by the virtual machines, attaches a destination switch address to the egress frame to be forwarded to the at least one physical switch, and receives and analyzes an ingress frame obtained from the at least one physical switch, so as to convert the destination switch address of the ingress frame to the destination machine address, for forwarding the ingress frame to one of the virtual machines.

Abstract: A network communication system comprises a cloud network and at least one physical machine. The cloud network comprises at least one physical switch. Each the physical machine comprises a plurality of virtual machines and a virtual switch. Each of the virtual machines is connected to the at least one physical switch in the cloud network through the virtual switch. The virtual switch encapsulates a destination machine address of an egress frame sent by the virtual machines, attaches a destination switch address to the egress frame to be forwarded to the at least one physical switch, and receives and analyzes an ingress frame obtained from the at least one physical switch, so as to convert the destination switch address of the ingress frame to the destination machine address, for forwarding the ingress frame to one of the virtual machines.

Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.