Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Abstract: Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

Abstract: Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

Abstract: An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 ?m.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Abstract: A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 ?m; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Abstract: An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 ?m.