Patents by Inventor SHIH-HSIANG CHIU
SHIH-HSIANG CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982866Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.Type: GrantFiled: December 15, 2022Date of Patent: May 14, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
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Patent number: 11961939Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.Type: GrantFiled: June 23, 2022Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11929263Abstract: The present disclosure provides a semiconductor manufacturing method and a system therefore. The semiconductor manufacturing method includes: providing a gas from a container through an outlet to a semiconductor wafer manufacturing equipment, wherein a control valve is connected to the outlet to control a gas flow; retrieving a set of parameters corresponding to the gas flow; and determining a nominal position of the control valve by incorporating the set of parameters through a processor in order to provide a desired flow passage into the semiconductor wafer manufacturing equipment, wherein the semiconductor wafer manufacturing equipment includes a plurality of independent reaction chambers, wherein each reaction chamber is individually supplied with a gas pipe, and each gas pipe receives the gas from the container.Type: GrantFiled: October 30, 2020Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hsiang Cheng, Shih Huan Chiu
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Patent number: 11862694Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: GrantFiled: April 6, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230411474Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: ApplicationFiled: August 7, 2023Publication date: December 21, 2023Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230369134Abstract: A method of manufacturing a semiconductor device is provided.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Liang Tai, Chun-Hsiang Fan, Ta-Wei Lin, Shih-Hsiang Chiu, Kuo-Bin Huang, Chieh-Chun Chiang
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Publication number: 20220406655Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.Type: ApplicationFiled: February 18, 2022Publication date: December 22, 2022Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220093758Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: ApplicationFiled: April 6, 2021Publication date: March 24, 2022Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 10510619Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.Type: GrantFiled: January 8, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Chang Lin, Shih-Hsiang Chiu, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
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Publication number: 20190157163Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.Type: ApplicationFiled: January 8, 2018Publication date: May 23, 2019Inventors: YU-CHANG LIN, SHIH-HSIANG CHIU, TIEN-SHUN CHANG, CHUN-FENG NIEH, HUICHENG CHANG