Patents by Inventor SHIH-HSIANG CHIU

SHIH-HSIANG CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278141
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12224327
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240387661
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11862694
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230411474
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Application
    Filed: August 7, 2023
    Publication date: December 21, 2023
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230369134
    Abstract: A method of manufacturing a semiconductor device is provided.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Tai, Chun-Hsiang Fan, Ta-Wei Lin, Shih-Hsiang Chiu, Kuo-Bin Huang, Chieh-Chun Chiang
  • Publication number: 20220406655
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.
    Type: Application
    Filed: February 18, 2022
    Publication date: December 22, 2022
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220093758
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Application
    Filed: April 6, 2021
    Publication date: March 24, 2022
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 10510619
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chang Lin, Shih-Hsiang Chiu, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Publication number: 20190157163
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 23, 2019
    Inventors: YU-CHANG LIN, SHIH-HSIANG CHIU, TIEN-SHUN CHANG, CHUN-FENG NIEH, HUICHENG CHANG