Patents by Inventor Shih-Hsien Lo
Shih-Hsien Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 10083880Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: April 24, 2017Date of Patent: September 25, 2018Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20170229353Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 9653615Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: March 13, 2013Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 9087909Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: GrantFiled: August 7, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20140264593Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporaitonInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Publication number: 20140264605Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.Type: ApplicationFiled: August 7, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
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Patent number: 8835997Abstract: A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.Type: GrantFiled: May 4, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Leland Chang, Chung-Hsun Lin, Shih-Hsien Lo, Jeffrey W. Sleight
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Patent number: 8835191Abstract: Methods for sensing a mechanical stress and methods of making stress sensor integrated circuits. The sensing methods include transferring the mechanical stress from the object to one or more nanowires in a stress sensor or stress sensor circuit and permitting the nanowires to change in length in response to the mechanical stress. An electrical characteristic of the stress sensor or stress sensor circuit, which has a variation correlated with changes in the magnitude of the mechanical stress, is measured and then assessed to determine the stress magnitude. The manufacture methods include electrically connecting nanowire field effect transistors having, as channel regions, one or more nanowires of either a different crystalline orientation or a different body width for the individual nanowires so that an offset output voltage results when mechanical strain is applied to the nanowires.Type: GrantFiled: February 11, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Andres Bryant, Oki Gunawan, Shih-Hsien Lo, Jeffrey W. Sleight
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Patent number: 8822295Abstract: A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.Type: GrantFiled: April 3, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Leland Chang, Chung-Hsun Lin, Shih-Hsien Lo, Jeffrey W. Sleight
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Patent number: 8614492Abstract: Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.Type: GrantFiled: October 26, 2009Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Andres Bryant, Oki Gunawan, Shih-Hsien Lo, Jeffrey W Sleight
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Publication number: 20130260525Abstract: A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.Type: ApplicationFiled: April 3, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Chung-Hsun Lin, Shih-Hsien Lo, Jeffrey W. Sleight
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Publication number: 20130256763Abstract: A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.Type: ApplicationFiled: May 4, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Chung-Hsun Lin, Shih-Hsien Lo, Jeffrey W. Sleight
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Patent number: 8526219Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: GrantFiled: February 7, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Publication number: 20130055183Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL P. BEAKES, SHIH-HSIEN LO, MICHAEL R. SCHEUERMANN, MATTHEW R. WORDEMAN
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Patent number: 8381156Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.Type: GrantFiled: August 25, 2011Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Michael P. Beakes, Shih-Hsien Lo, Michael R. Scheuermann, Matthew R. Wordeman
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Publication number: 20120185817Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: ApplicationFiled: February 7, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Patent number: 8139400Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: GrantFiled: January 22, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Publication number: 20110095267Abstract: Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Applicant: International Business Machines CorporationInventors: Andres Bryant, Oki Gunawan, Shih-Hsien Lo, Jeffrey W. Sleight
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Publication number: 20090185409Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao