Abstract: A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.

Abstract: A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

Abstract: A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit.

Abstract: A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

Abstract: A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit.

Abstract: A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

Abstract: A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.

Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration.

Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue.

Abstract: One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.

Abstract: A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line.

Abstract: Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.