Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.

Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Abstract: A serial bidirectional communication method is provided. The method includes: performing a downlink transmission and performing an uplink transmission. The downlink transmission includes: receiving first downlink data through a first transmission terminal, wherein the first downlink data comprises at least one control command, and the at least one control command is cascaded and configured to control at least one electronic device; removing one, corresponding to a local device, of the at least one control command from the first downlink data to form second downlink data, wherein the local device is one of the at least one electronic device; and when there is a control command remaining in the second downlink, outputting the second downlink data through a second transmission terminal. The uplink transmission includes outputting first uplink data through the first transmission terminal. The first uplink data includes local information generated by the local device.

Abstract: A serial bidirectional communication method is provided. The method includes: performing a downlink transmission and performing an uplink transmission. The downlink transmission includes: receiving first downlink data through a first transmission terminal, wherein the first downlink data comprises at least one control command, and the at least one control command is cascaded and configured to control at least one electronic device; removing one, corresponding to a local device, of the at least one control command from the first downlink data to form second downlink data, wherein the local device is one of the at least one electronic device; and when there is a control command remaining in the second downlink, outputting the second downlink data through a second transmission terminal. The uplink transmission includes outputting first uplink data through the first transmission terminal. The first uplink data includes local information generated by the local device.

Abstract: A fan detection method, a fan detection chip and a fan detection system using the same are disclosed. The fan detection method is applied to a fan detection chip including a first pin, a second pin, a third pin, a fourth pin, and the fan is electrically coupled to the first pin, the second pin and the third pin at least. The fan detection method includes following steps: controlling a switch to selectively conduct the first pin and the second pin; controlling a pulse width modulation (PWM) signal processing module to output a voltage pulse to the fourth pin; detecting, by the voltage detection module, a voltage level on the fourth pin; and determining the fan to be a PWM fan when the voltage level is changed, and determining the fan to be a DC fan when the voltage level is not changed.

Abstract: A fan detection method, a fan detection chip and a fan detection system using the same are disclosed. The fan detection method is applied to a fan detection chip including a first pin, a second pin, a third pin, a fourth pin, and the fan is electrically coupled to the first pin, the second pin and the third pin at least. The fan detection method includes following steps: controlling a switch to selectively conduct the first pin and the second pin; controlling a pulse width modulation (PWM) signal processing module to output a voltage pulse to the fourth pin; detecting, by the voltage detection module, a voltage level on the fourth pin; and determining the fan to be a PWM fan when the voltage level is changed, and determining the fan to be a DC fan when the voltage level is not changed.

Abstract: A power management circuit is provided. The power management circuit includes a power switch, a current/voltage detector, a current setting unit, and a control unit. The power switch is coupled to a power supply of the computer system. When the power switch is turned on, it supplies an output current and an output voltage of the power supply to an external device. The current/voltage detector detects the magnitudes of the output current and the output voltage. The current setting unit sets a plurality of current thresholds. When the computer system is in a power-saving state and when the output current is greater than a first current threshold and smaller than a second current threshold or the output voltage is smaller than a first voltage threshold and larger than a second voltage threshold, the control unit issues a notification signal to execute a predetermined operation on the power supply.

Abstract: A video processing system is provided. A video signal processor receives a video signal, processes the video signal to obtain video images and program information and stores the program information in a program information buffer. A microprocessor issues an on screen display (OSD) paint command and accesses the program information buffer to obtain the program information. An OSD control module receives the OSD paint command and acquires the program information from the microprocessor, and converts the program information and initial attributes to form an OSD image in response to the OSD paint command.

Abstract: Systems and methods may determine a boundary value data unit in a large data set in parallel with determining an associated index of the determined boundary value data unit into the large data set using a single instruction multiple data (SIMD) instruction set architecture and a specialized data layout of array entries. In one example, the specialized data layout of array entries combines a data value and its associated index to an array into a single array entry.

Abstract: Systems and methods may determine a boundary value data unit in a large data set in parallel with determining an associated index of the determined boundary value data unit into the large data set using a single instruction multiple data (SIMD) instruction set architecture and a specialized data layout of array entries. In one example, the specialized data layout of array entries combines a data value and its associated index to an array into a single array entry.

Abstract: A power management circuit is provided. The power management circuit includes a power switch, a current/voltage detector, a current setting unit, and a control unit. The power switch is coupled to a power supply of the computer system. When the power switch is turned on, it supplies an output current and an output voltage of the power supply to an external device. The current/voltage detector detects the magnitudes of the output current and the output voltage. The current setting unit sets a plurality of current thresholds. When the computer system is in a power-saving state and when the output current is greater than a first current threshold and smaller than a second current threshold or the output voltage is smaller than a first voltage threshold and larger than a second voltage threshold, the control unit issues a notification signal to execute a predetermined operation on the power supply.

Abstract: A video processing system is provided. A video signal processor receives a video signal, processes the video signal to obtain video images and program information and stores the program information in a program information buffer. A microprocessor issues an on screen display (OSD) paint command and accesses the program information buffer to obtain the program information. An OSD control module receives the OSD paint command and acquires the program information from the microprocessor, and converts the program information and initial attributes to form an OSD image in response to the OSD paint command.

Abstract: A pulse width modulation (PWM) circuit and a method for enabling the same are provided. The method includes the steps of: receiving a first power voltage and a second power voltage; providing a high-side driving power pin, wherein the peripheral circuit of the high-side driving power pin is adapted for generating a high-side driving voltage according to the first power voltage and the second power voltage; and enabling the PWM circuit when the high-side driving voltage is larger than the second power voltage.

Abstract: A supply-independent biasing circuit applied to a bandgap reference circuit or a proportional to absolute temperature (PTAT) current generating circuit. The bandgap reference circuit or the PTAT current generating circuit includes a mirroring circuit, an operation amplifier, and an input circuit. The mirroring circuit including a plurality of first type FETs. The operation amplifier includes a first type FET connecting to a current input terminal of the operation amplifier. And, the supply-independent biasing circuit includes a first type FET having a gate connected to gates of the first type FETs in the mirroring circuit and having a drain acted as an output current path; and, a current mirror including a plurality of second type FETs and having a current receiving terminal connected to the output current path and having a current outputting terminal connected to the current input terminal of the operation amplifier.