Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

Abstract: A shift register includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch for generating a first output signal according to a clock signal while the first switch is turned on, and a second switch coupled to an output end of the shift register for generating and transmitting a second output signal to the output end of the shift register according to the clock signal while the second switch is turned on. The driving circuit is for controlling the first and second switches according to an input signal received from an input end of the shift register. The reset circuit is for turning off the first and second switches and resetting the output signal outputted by the output end. The control switch is for resetting the output signal outputted by the output end.

Abstract: A control circuit equipped with electrostatic discharge (ESD) protection includes a plurality of shift registers, a plurality of buses coupled to the plurality of shift registers, a common line, a set of ESD protection components coupled to a set of the plurality of the buses for protecting the plurality of buses from ESD events; and a set of current paths coupled between the set of the ESD protection components and the common line for providing the ESD current paths to pass through.

Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.

Abstract: A liquid crystal display and a shift register unit thereof are provided. The shift register unit includes a first switch, a second switch, and a level shift circuit. The first switch has a first input terminal, a first control terminal, and a first output terminal. The second switch has a second input terminal, a second control terminal, and a second output terminal. The second control terminal is coupled to the first output terminal and the level shift circuit. When the first switch is enabled, the first input terminal receives an input signal converting the voltage of the second control terminal into a first voltage for turning on the second switch. The second output terminal outputs a first clock signal to a scan signal line. When the level shift circuit is enabled, the voltage of the second control terminal is converted into a second voltage for turning off the second switch.

Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.