Abstract: A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC.