Patents by Inventor Shih-Hung Lan
Shih-Hung Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9363115Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.Type: GrantFiled: July 2, 2012Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Yu Hsu, Ruey-Bin Sheen, Shih-Hung Lan, Chih-Hsien Chang
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Patent number: 9350324Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.Type: GrantFiled: December 27, 2012Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 9098757Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.Type: GrantFiled: June 25, 2013Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8937842Abstract: A strobe calibration component for a memory control device includes a tri-state detection receiver, an edge detection component, and an extension gate generation component. The tri-state detection receiver is configured to identify states of an input signal. One of the states includes a high impedance state. The edge detection component is configured to identify valid edges from a sequence of states provided from the tri-state detection receiver. The extension gate generation component is configured to generate a calibrated gate signal according to the valid edges from the edge detection component.Type: GrantFiled: November 5, 2012Date of Patent: January 20, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ruey-Bin Sheen, Tien-Chien Huang, Shih-Hung Lan
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Publication number: 20140184296Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-Ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20140145749Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.Type: ApplicationFiled: June 25, 2013Publication date: May 29, 2014Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20140126310Abstract: A strobe calibration component for a memory control device includes a tri-state detection receiver, an edge detection component, and an extension gate generation component. The tri-state detection receiver is configured to identify states of an input signal. One of the states includes a high impedance state. The edge detection component is configured to identify valid edges from a sequence of states provided from the tri-state detection receiver. The extension gate generation component is configured to generate a calibrated gate signal according to the valid edges from the edge detection component.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ruey-Bin Sheen, Tien-Chien Huang, Shih-Hung Lan
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Publication number: 20140006883Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.Type: ApplicationFiled: July 2, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Yu HSU, Ruey-Bin SHEEN, Shih-Hung LAN, Chih-Hsien CHANG
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Patent number: 8327213Abstract: A data receiving method for an electronic system including a host apparatus and a target apparatus, wherein the host apparatus transmits at least one request to the target apparatus for requesting at least one desired data, and the target apparatus transmits the desired data to the host apparatus according to the request. The data receiving method includes: (a) generating a statistic value according to a number of the requests; (b) varying the statistic value according to a number of the desired data; and (c) determining if data received by the host apparatus is the desired data corresponding to the request according to the static value, and storing the data received by the host apparatus to the host apparatus when the data received by the host apparatus is determined to be the desired data corresponding to the request.Type: GrantFiled: May 6, 2010Date of Patent: December 4, 2012Assignee: Silicon Motion Inc.Inventor: Shih-Hung Lan
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Publication number: 20110072337Abstract: A data receiving method for an electronic system including a host apparatus and a target apparatus, wherein the host apparatus transmits at least one request to the target apparatus for requesting at least one desired data, and the target apparatus transmits the desired data to the host apparatus according to the request. The data receiving method comprises: (a) generating a statistic value according to a number of the requests; (b) varying the statistic value according to a number of the desired data; and (c) determining whether data received by the host apparatus is the desired data corresponding to the request or not according to the static value, to thereby determine whether the data received by the host apparatus is stored to the host apparatus or not.Type: ApplicationFiled: May 6, 2010Publication date: March 24, 2011Inventor: Shih-Hung Lan
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Publication number: 20110004784Abstract: A data accessing method applied to a data accessing system, comprising: (a) performing a logic operation to a plurality of data units to generate at least one logic operation data unit; (b) performing an anti logic operation to the logic operation data unit and an other data unit to obtain a recovery data unit wherein the other data unit comprises the data units except a specific data unit in the data units; and (c) replacing the specific data unit with the recovery data unit, when the specific data unit is read and is found having an error.Type: ApplicationFiled: April 5, 2010Publication date: January 6, 2011Inventors: Shih-Hung Lan, Sheng-I Hsu