Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: Disclosed is a method for testing a semiconductor element. The method comprises forming at least one redistribution layer on a chip, utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip, and removing the at least one redistribution layer from the chip, wherein the length of each semiconductor element is between 2-150 ?m and the width of each semiconductor element is between 2-150 ?m.

Abstract: The present invention provides a patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first patent classification code data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction based on at least the first search criterion instruction and the first patent classification code data item, the second search criterion instruction including the first patent classification code data item, wherein the server retrieves a plurality of t

Abstract: A patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first keyword data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction at least based on the first search criterion instruction and the first keyword data item, the second search criterion instruction comprising the first keyword data item, wherein the server retrieves a plurality of third patent document data items from the plurality of first patent document data items

Abstract: Disclosed is a method for testing a semiconductor element. The method comprises forming at least one redistribution layer on a chip, utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip, and removing the at least one redistribution layer from the chip, wherein the length of each semiconductor element is between 2-150 ?m and the width of each semiconductor element is between 2-150 ?m.

Abstract: A device for bone fixation comprises an expansion part and a covering part. The expansion part has a fixing end and a top end and provides an expansion structure for being adjustable between a state of expansion and contraction. The covering part has a front end and a joining end, wherein the front end thereof is joined to the top end of the expansion part, and the joining end thereof is attached to the fixing end of the expansion part. The covering part is employed to cover the expansion structure. After the expansion part and the covering part are added to the bone, the covering part is unfurled to spread to the expansion state, and the medical filler is injected or pushed into the covering part.

Abstract: A method for making the composite material wheel rim includes the steps of: configuring a plurality of inner lining chunks individually to the desired position where the spokes are to be mounted to allow the inner lining chunks to be integrated with an inner annular portion of the wheel rim, next, integrating the formed inner annular portion with an outer annular portion of the wheel rim to form a semi-finished wheel rim, and then, creating the requested threaded holes for connecting the spokes in the inner lining chunks of the inner surface of the semi-finished wheel rim subject to the requested amount and angles of the spokes. By the present method, the semi-finished wheel rim allows drilled, threaded holes subject to needs to fit different types of wheel hub units to increase the yield rate and reduce the inventory of the wheel rims.

Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.

Abstract: An inductive breathing mask is provided, which comprises a covering shell, a mask pad, and a pressure inductive unit, wherein the pressure inductive unit comprising at least one pressure inductive part, and the pressure inductive part is disposed on the mask pad where corresponds to at least one of the user's nasion, left cheek beside nose, right cheek beside nose, and chin for detecting the pressure of the user's nasion, left cheek beside nose, right cheek beside nose, and chin generated by the mask pad. In addition, the inductive breathing mask of the present invention may further be integrated with other functional elements for constructing a respiratory care system having warning and/or monitoring functions.