Abstract: A signal quality optimization system and a signal quality optimization method are provided.

Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: The present invention provides an electronic device including a storage device and a processor. The storage device includes a program code and a database, wherein the database includes a plurality of combinations of printed circuit boards and packages and a plurality of channel models. The processor is configured to execute the program code to perform the steps of: obtaining a first combination of the plurality of combinations of printed circuit boards and packages from the database; obtaining a first channel model of the plurality of channel models from the database, wherein the first channel model is generated according to the first combination; determining first die information; and performing simulation to generate characteristics of a power delivery network and a voltage drop of a system according to the first channel model and the first die information.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: An electronic system test method, comprising: (a)inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b)acquiring a output response corresponding to the step (a); and (c)after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Abstract: The present invention relates to a method of manufacturing a liquid crystal display (LCD) of the polymer stabilized ultra fast (PS-UF) twisted nematic (TN) mode, to an LCD obtained by this method and to an LC medium used therein.

Abstract: A floating nail guide gun nozzle for nail a gun has a nail gun body, a gun nozzle holder located in the front end of the nail gun body, a linked cover plate located on the gun nozzle holder and an elastic reset mechanism located on the gun nozzle holder. A strutting bulge protrudes from the bottom surface of the front end of the linked cover plate, and the strutting bulge flares towards the front end of the linked cover plate and tilts down. The elastic reset mechanism enables the linking part to prop the strutting bulge of the linked cover plate against the gun nozzle holder without an external force.

Abstract: A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.

Abstract: An electronic apparatus having noise suppression mechanism is provided that includes a circuit board, a wireless communication circuit, a digital signal generation circuit, a metal shield and a grounding metal pillar. The wireless communication circuit is disposed on a chip disposing area of the circuit board and performs wireless communication within a wireless signal frequency range. The digital signal generation circuit is disposed on the chip disposing area and generates a digital signal transmitted through a transmission path within the chip disposing area. The metal shield is coupled to the circuit board to cover the chip disposing area. The grounding metal pillar is disposed on the chip disposing area of the circuit board. The grounding metal pillar extends for contacting the metal shield and increases a resonant frequency of the metal shield.

Abstract: A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: A winding structure of a stator and an electric machinery using the stator are disclosed. The winding structure includes a first magnetic pole, a second magnetic pole, a third magnetic pole, a fourth magnetic pole, a fifth magnetic pole, a sixth magnetic pole, a seventh magnetic pole and an eighth magnetic pole which are arranged in a circumferential direction. The first to eighth magnetic poles are wound with first to eight windings, respectively. Each of the first to eight windings has a number of turns, and the numbers of turns of the first to eight windings are in ratios 1:8:3:4:9:2:7:6. The first to eighth windings have a total number of turns of “40n,” and wherein 40n?720 As such, the electricity generation efficiency of the electric machinery can be improved.

Abstract: The present invention relates to a method of manufacturing a photovoltaic device having an ultra-shallow junction layer. In the method, a crystalline silicon substrate is cleaned and a first doped semiconductor layer with 1.12 eV bandgap and 5˜80 nm of thickness is grown on the crystalline silicon substrate by high density plasma electron cyclotron resonance CVD in a preparation condition of a temperature of the crystalline silicon substrate ranging from 50° C. to 250° C. , about 500W of microwave power, deposition pressure below 50 mTorr, about 20 sccm of argon and hydrogen flow rate, SiH4 flow rate ranging from 1 sccm to 2 sccm, and 2% boroethane flow rate ranging from about 5 seem to 15 sccm. The photovoltaic device of the present invention has advantages of abrupt homo-junction, ultra-thin high-crystallinity silicon-based thin film, highly-doped concentration, high conductivity and high short-circuit current, thereby having improved efficiency.

Abstract: A winding structure of a stator and an electric machinery using the stator are disclosed. The winding structure includes a first magnetic pole, a second magnetic pole, a third magnetic pole, a fourth magnetic pole, a fifth magnetic pole, a sixth magnetic pole, a seventh magnetic pole and an eighth magnetic pole which are arranged in a circumferential direction. The first to eighth magnetic poles are wound with first to eight windings, respectively. Each of the first to eight windings has a number of turns, and the numbers of turns of the first to eight windings are in ratios 1:8:3:4:9:2:7:6. The first to eighth windings have a total number of turns of “40n,” and wherein 40n?720 As such, the electricity generation efficiency of the electric machinery can be improved.

Abstract: A control circuit for a peripheral component interconnect express (PCI-E) device includes a power detecting unit and a parameter adjustment unit. The power detecting unit is coupled to a wireless communication transmitter, and arranged to detect a spectrum intensity value of an output spectrum of the wireless communication transmitter. The parameter adjustment unit is coupled to the power detecting unit, and arranged to produce at least one control signal according to the spectrum intensity value and adaptively adjust a parameter setting of the PCI-E device in accordance with the at least one control signal.

Abstract: A yellow dye compound having a structure of following formula (I) is disclosed: wherein R1, R2, R3, and R4, is defined the same as in the specification. The yellow dye compound can be used in ink-jet ink. Also disclosed is a yellow ink composition including the yellow dye compound having the above formula (I).