Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

Abstract: The present invention is related to a display device, including: a plurality of sub-pixel areas, each including a sub-pixel circuit, each sub-pixel circuit including: a diode, configured to be in a forward-biasing state during a displaying phase of the sub-pixel circuit for emitting light and configured to be in a reverse-biasing state for sensing light of the sub-pixel circuit in a sensing phase; a driving transistor for driving the diode during the display phase; first to sixth transistors, gate control signals are applied to gates of the first to sixth transistors respectively, so that the sub-pixel circuit switching between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase, wherein in the sensing phase the diode generates a photocurrent to an operational amplifier, such that the operational amplifier outputs a photocurrent output signal.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: The present invention provides an electronic device including a storage device and a processor. The storage device includes a program code and a database, wherein the database includes a plurality of combinations of printed circuit boards and packages and a plurality of channel models. The processor is configured to execute the program code to perform the steps of: obtaining a first combination of the plurality of combinations of printed circuit boards and packages from the database; obtaining a first channel model of the plurality of channel models from the database, wherein the first channel model is generated according to the first combination; determining first die information; and performing simulation to generate characteristics of a power delivery network and a voltage drop of a system according to the first channel model and the first die information.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: An electronic system test method, comprising: (a)inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b)acquiring a output response corresponding to the step (a); and (c)after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: An electromagnetic band gap structure apparatus includes a first conducting layer having at least one first slot. Each of the at least one slot is arranged with a planar conductor unit, and the each planar conductor unit is coupled to a first via. The electromagnetic band gap structure apparatus further includes a second conducting layer in parallel with the first conducting layer. The second conducting layer has a second slot. The second slot is arranged with at least one planar transmission line unit. The each of the at least one planar transmission line unit is coupled to the first conducting layer through a second via, and the each first via is coupled to the second conducting layer.

Abstract: The present invention relates to a method of manufacturing a liquid crystal display (LCD) of the polymer stabilized ultra fast (PS-UF) twisted nematic (TN) mode, to an LCD obtained by this method and to an LC medium used therein.

Abstract: A floating nail guide gun nozzle for nail a gun has a nail gun body, a gun nozzle holder located in the front end of the nail gun body, a linked cover plate located on the gun nozzle holder and an elastic reset mechanism located on the gun nozzle holder. A strutting bulge protrudes from the bottom surface of the front end of the linked cover plate, and the strutting bulge flares towards the front end of the linked cover plate and tilts down. The elastic reset mechanism enables the linking part to prop the strutting bulge of the linked cover plate against the gun nozzle holder without an external force.

Abstract: A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.

Abstract: An electronic apparatus having noise suppression mechanism is provided that includes a circuit board, a wireless communication circuit, a digital signal generation circuit, a metal shield and a grounding metal pillar. The wireless communication circuit is disposed on a chip disposing area of the circuit board and performs wireless communication within a wireless signal frequency range. The digital signal generation circuit is disposed on the chip disposing area and generates a digital signal transmitted through a transmission path within the chip disposing area. The metal shield is coupled to the circuit board to cover the chip disposing area. The grounding metal pillar is disposed on the chip disposing area of the circuit board. The grounding metal pillar extends for contacting the metal shield and increases a resonant frequency of the metal shield.

Abstract: A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.