Abstract: A heart rate detection method for calculating heart rate using heart sound from auscultation positions identified by a statistical approach utilizes a down-sampling and filtering process to acquire samples of heart sound from multiple auscultation positions of multiple testees and calculate heart rate with the samples, records time for calculating heart rate from each auscultation position of each testee and record the same from electrocardiogram, calculates a mean error and a standard deviation of the time to identify the auscultation positions allowing faster speed in heart rate detection, and applies a Bland-Altman difference plot and both a coefficient of determination and a Pearson's correlation coefficient to determine the degree of consistency and correlation of the heart rate measured from the multiple auscultation positions to identify the auscultation positions allowing generation of precise heart rate.

Abstract: A system for recognizing physiological sound comprises a receiving module, a feature extracting module, a classifier, and a comparing module. A method for recognizing physiological sound comprises receiving a physiological sound by the receiving module; extracting at least one feature from the physiological sound by the feature extraction module; classifying the at least one feature to identify at least one category by a classifier; and comparing the at least one category with a normal physiological sound and/or an abnormal physiological sound by the comparing module for evaluating a risk of disease. The method and system for recognizing physiological sound can precisely identify the specific physiological sound and exclude the noise.

Abstract: A heart rate detection method for calculating heart rate using heart sound from auscultation positions identified by a statistical approach utilizes a down-sampling and filtering process to acquire samples of heart sound from multiple auscultation positions of multiple testees and calculate heart rate with the samples, records time for calculating heart rate from each auscultation position of each testee and record the same from electrocardiogram, calculates a mean error and a standard deviation of the time to identify the auscultation positions allowing faster speed in heart rate detection, and applies a Bland-Altman difference plot and both a coefficient of determination and a Pearson's correlation coefficient to determine the degree of consistency and correlation of the heart rate measured from the multiple auscultation positions to identify the auscultation positions allowing generation of precise heart rate.

Abstract: A system for recognizing physiological sound comprises a receiving module, a feature extracting module, a classifier, and a comparing module. A method for recognizing physiological sound comprises receiving a physiological sound by the receiving module; extracting at least one feature from the physiological sound by the feature extraction module; classifying the at least one feature to identify at least one category by a classifier; and comparing the at least one category with a normal physiological sound and/or an abnormal physiological sound by the comparing module for evaluating a risk of disease. The method and system for recognizing physiological sound can precisely identify the specific physiological sound and exclude the noise.

Abstract: An image sensor device with layered structures is disclosed, which includes a carrier wafer, image sensing structures and insulating layers. The carrier wafer has a pixel area and a peripheral area. Each of the image sensing structures has a first portion in the pixel area for sensing incident light in a specific wavelength band and a second portion in the peripheral area. Each of the insulating layers is disposed between adjacent stacked image sensing structures, such that crosstalk issues between adjacent diffusion layers are avoided for higher isolation, thereby improving photo sensing quality.

Abstract: An image sensor device with layered structures is disclosed, which includes a carrier wafer, image sensing structures and insulating layers. The carrier wafer has a pixel area and a peripheral area. Each of the image sensing structures has a first portion in the pixel area for sensing incident light in a specific wavelength band and a second portion in the peripheral area. Each of the insulating layers is disposed between adjacent stacked image sensing structures, such that crosstalk issues between adjacent diffusion layers are avoided for higher isolation, thereby improving photo sensing quality.

Abstract: An image sensor device with layered structures is disclosed, which includes a carrier wafer, image sensing structures and insulating layers. The carrier wafer has a pixel area and a peripheral area. Each of the image sensing structures has a first portion in the pixel area for sensing incident light in a specific wavelength band and a second portion in the peripheral area. Each of the insulating layers is disposed between adjacent stacked image sensing structures, such that crosstalk issues between adjacent diffusion layers are avoided for higher isolation, thereby improving photo sensing quality.

Abstract: Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate.

Abstract: Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate.

Abstract: A vertical array of flash memory cells. Transistor bodies are disposed on a substrate, comprising a source, channel and drain region, stacked thereon. Two joint gate structures are disposed on opposite sidewalls of every two transistor bodies respectively, and include a joint tunnel oxide layer disposed conformally on sidewalls of the two transistor bodies and the substrate there between, two floating gates on the opposite sidewalls of the tunnel oxide layer, a joint insulating layer covering the floating gates and the substrate there between, and a joint control gate layer on the sidewalls of the transistor bodies and the substrate there between. A dielectric layer covers the transistor bodies, where bit lines and word lines are disposed therein in contact with the top surfaces of the transistor bodies and the control gates between every two transistor bodies respectively. Source lines are disposed in the substrate to contact the source regions.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.

Abstract: A vertical array of flash memory cells. Transistor bodies are disposed on a substrate, comprising a source, channel and drain region, stacked thereon. Two joint gate structures are disposed on opposite sidewalls of every two transistor bodies respectively, and include a joint tunnel oxide layer disposed conformally on sidewalls of the two transistor bodies and the substrate there between, two floating gates on the opposite sidewalls of the tunnel oxide layer, a joint insulating layer covering the floating gates and the substrate there between, and a joint control gate layer on the sidewalls of the transistor bodies and the substrate there between. A dielectric layer covers the transistor bodies, where bit lines and word lines are disposed therein in contact with the top surfaces of the transistor bodies and the control gates between every two transistor bodies respectively. Source lines are disposed in the substrate to contact the source regions.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.