Abstract: A control circuit of a communication device includes: a periodic packet detection circuit, detecting a periodic packet of a data signal to generate a packet indication signal corresponding to the periodic packet; a frequency synthesis circuit, coupled to the periodic packet detection circuit, generating a working clock according to a reference clock; and a setting value generating circuit, coupled to the periodic packet detection circuit, generating a setting value according to a relationship between the frequencies of the working clock and the packet indication signal. The frequency synthesis circuit further adjusts the working clock according to the setting value to cause the frequency of the working clock to substantially be a predetermined multiple of the frequency of the packet indication signal.

Abstract: An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.

Abstract: A control circuit of a communication device includes: a periodic packet detection circuit, detecting a periodic packet of a data signal to generate a packet indication signal corresponding to the periodic packet; a frequency synthesis circuit, coupled to the periodic packet detection circuit, generating a working clock according to a reference clock; and a setting value generating circuit, coupled to the periodic packet detection circuit, generating a setting value according to a relationship between the frequencies of the working clock and the packet indication signal. The frequency synthesis circuit further adjusts the working clock according to the setting value to cause the frequency of the working clock to substantially be a predetermined multiple of the frequency of the packet indication signal.

Abstract: A multi-mode output transmitter includes a pair of driving circuits and a pair of common circuits. Each of the driving circuits includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and each of the common circuits includes a p-channel MOSFET. In one transmission mode, one of the pair of common circuits and one of the pair of driving circuits complementarily conduct; and in another transmission mode, the pair of common circuits simultaneously conduct to provide termination resistors.