Patents by Inventor Shih-Kai FAN
Shih-Kai FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230213457Abstract: An automated optical double-sided inspection apparatus includes a first image-capturing portion, a second image-capturing portion, a platform, a first light-blocking portion, a second light-blocking portion, and a processing portion. The platform carries an external object. When the processing portion operates in a first capturing mode, the second light-blocking portion blocks visible light from passing therethrough, while the first light-blocking portion allows visible light to pass therethrough, so that the first image-capturing portion shoots a first side of the external object through the first light-blocking portion to obtain a first image.Type: ApplicationFiled: December 21, 2022Publication date: July 6, 2023Inventors: Yee Siang GAN, Sze-Teng LIONG, Shih-Kai FAN, Che-Ming LI, Yu-Hsien LIN
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Publication number: 20230210102Abstract: An intelligent Forcipomyia taiwana monitoring and management system comprises: a catching mechanism grabbing a to-be-identified target; a database storing a datum comprising pictures of a flying insect category; a model training module using the pictures to establish a training model; an image capture module shooting an image including the target; an identifying module selecting a first segmented region including the target by using YOLO detection framework technology, extracting a first identification feature from the target, and inputting the feature into the training model for deep learning to identify a flying insect category to which the target belongs and produce an identification result; a counting module recording a number of the target into the database; and a predictive tracking module obtaining a marked object based on the result marked with the target identified in the image, and using a Monte-Carlo category algorithm to track and predict the object.Type: ApplicationFiled: December 21, 2022Publication date: July 6, 2023Inventors: Yee Siang GAN, Shih-Kai FAN, Ching-Yun TSENG, Sze-Teng LIONG, Yu-Ting SHENG
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Patent number: 11094579Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.Type: GrantFiled: May 26, 2020Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
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Publication number: 20200286774Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: Yen-Bin HUANG, Chien-Mao CHEN, Yu-Hsuan KUO, Shih-Kai FAN, Chia-Hung LAI, Kang-Min KUO
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Patent number: 10699938Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.Type: GrantFiled: July 18, 2013Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
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Patent number: 10008494Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: GrantFiled: January 11, 2017Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen
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Publication number: 20170125417Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: ApplicationFiled: January 11, 2017Publication date: May 4, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh LAI, Kuang-Hsin CHEN, Shih-Kai FAN, Yung-Hsien WU, Yu-Hsun CHEN
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Patent number: 9570568Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: GrantFiled: May 28, 2015Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen
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Publication number: 20160351673Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: ApplicationFiled: May 28, 2015Publication date: December 1, 2016Inventors: Cheng-Chieh LAI, Kuang-Hsin CHEN, Shih-Kai FAN, Yung-Hsien WU, Yu-Hsun CHEN
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Publication number: 20150021700Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.Type: ApplicationFiled: July 18, 2013Publication date: January 22, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Bin HUANG, Chien-Mao CHEN, Yu-Hsuan KUO, Shih-Kai FAN, Chia-Hung LAI, Kang-Min KUO