Patents by Inventor Shih-Kai Huang
Shih-Kai Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154021Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.Type: ApplicationFiled: December 29, 2022Publication date: May 9, 2024Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
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Publication number: 20240105815Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.Type: ApplicationFiled: March 27, 2023Publication date: March 28, 2024Inventors: Chin-Yi HUANG, Shih Chan WEI, Wei Kai SHIH
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Publication number: 20240073555Abstract: The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results.Type: ApplicationFiled: July 20, 2023Publication date: February 29, 2024Inventors: SHENG-KAI CHEN, HUI-CHUN LIEN, WEN-TSUNG HUANG, SHIH-HSIANG YEN, SZU-PO HUANG
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Patent number: 10769811Abstract: A space coordinate converting server and method thereof are provided. The space coordinate converting server receives a field video recorded with a 3D object from an image capturing device, and generates a point cloud model accordingly. The space coordinate converting server determines key frames of the field video, and maps the point cloud model to key images of the key frames based on rotation and translation information of the image capturing device for generating a characterized 3D coordinate set. The space coordinate converting server determines 2D coordinates of the 3D object in key images, and selects 3D coordinates from the characterized 3D coordinate set according to the 2D coordinates. The space coordinate converting server determines a space coordinate converting relation according to marked points of the 3D object and the 3D coordinates.Type: GrantFiled: July 30, 2018Date of Patent: September 8, 2020Assignee: Institute For Information IndustryInventors: Jia-Wei Hong, Shih-Kai Huang, Ming-Fang Weng, Ching-Wen Lin
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Publication number: 20200058435Abstract: An inductor structure with height limit, which comprises: a conductor formed in a bent shape, and is set with a plurality of bending-portions, wherein a first connecting-pin and a second connecting-pin are respectively set at two ends of the conductor; a first magnetic core set with a first combining-surface, wherein the first combining-surface forms a concave groove to accommodate the conductor; and a second magnetic core set with a second combining-surface, wherein the second combining-surface forms a second concave groove to accommodate the conductor; wherein the second combining-surface is combined on the first combining-surface; wherein the conductor is sheathed and set between the first magnetic core and the second magnetic core, and is set with the first connecting-pin and the second connecting-pin exposedly. Therefore, the present invention can increase the magnetic (coupling) route length under the height limit to produce an effect of increasing the inductance value and current.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Chien-Chin Chang, Yu-Ting Hsu, Hung-Chih Liang, Shih-Kai Huang, Yen-Chun Wu
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Publication number: 20200013187Abstract: A space coordinate converting server and method thereof are provided. The space coordinate converting server receives a field video recorded with a 3D object from an image capturing device, and generates a point cloud model accordingly. The space coordinate converting server determines key frames of the field video, and maps the point cloud model to key images of the key frames based on rotation and translation information of the image capturing device for generating a characterized 3D coordinate set. The space coordinate converting server determines 2D coordinates of the 3D object in key images, and selects 3D coordinates from the characterized 3D coordinate set according to the 2D coordinates. The space coordinate converting server determines a space coordinate converting relation according to marked points of the 3D object and the 3D coordinates.Type: ApplicationFiled: July 30, 2018Publication date: January 9, 2020Inventors: Jia-Wei HONG, Shih-Kai HUANG, Ming-Fang WENG, Ching-Wen LIN
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Patent number: 10522281Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.Type: GrantFiled: March 14, 2018Date of Patent: December 31, 2019Assignee: MAG. LAYERS SCIENTIFIC-TECHNICS CO., LTD.Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Shih-Kai Huang, Chien-Chin Chang, Hung-Chih Liang, Yu-Ting Hsu
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Publication number: 20190287708Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Shih-Kai Huang, Chien-Chin Chang, Hung-Chih Liang, Yu-Ting Hsu
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Publication number: 20100131808Abstract: A memory testing method is provided, by using the computation capability of a controller to receive the testing command the program code of a testing PC to generate random data or use an algorithm to generate testing data of specific format. Then, the method writes the data directly to the flash memory and read the data from the memory again to compare with the original data. The comparison result is transmitted back to the testing PC. The method greatly reduces the memory access frequency and I/O load of the testing PC so as to improve the testing efficiency.Type: ApplicationFiled: November 25, 2008Publication date: May 27, 2010Inventors: Bei-Chuan Chen, Li-Hsiang Chan, Shih-Kai Huang
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Publication number: 20090157999Abstract: A control mechanism for multi-functional chips is provided. By receiving operation signals from the predefined pins of the different operation functions, the present invention accesses the corresponding storage area in the memory module according to the operation signals without using different memory modules and memory controllers corresponding to different operation functions so as to save power and reduce the hardware size. For example, the MegaSIMâ„¢ multi-functional chip includes the integration of a plurality of operation functions, such as SD/MMC and ISO 7816. Each operation function uses different communication protocol to provide operation signals through individual to shared predefined pins. For example, MegaSIMâ„¢ I/O, Vpp/CLK, GND, CLK RST, and Vcc pins are used by ISO 7816, and Cmd, Data0, and Vpp/CLK pins are used by SD/MMC.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Inventors: Bei-Chuan Chen, Li-Hsiang Chan, Shih-Kai Huang