Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A common mode filter includes a first iron core, a second iron core, a first coil, and a second coil. The first iron core includes two first electrode portions and two second electrode portions. The second iron core is disposed above the first iron core, and the first iron core and the second iron core are adhered to each other. All surfaces of the second iron core are coated with an insulating layer. The first coil is wound around the first iron core and the second iron core. The second coil is wound around the first iron core and the second iron core.

Abstract: A space coordinate converting server and method thereof are provided. The space coordinate converting server receives a field video recorded with a 3D object from an image capturing device, and generates a point cloud model accordingly. The space coordinate converting server determines key frames of the field video, and maps the point cloud model to key images of the key frames based on rotation and translation information of the image capturing device for generating a characterized 3D coordinate set. The space coordinate converting server determines 2D coordinates of the 3D object in key images, and selects 3D coordinates from the characterized 3D coordinate set according to the 2D coordinates. The space coordinate converting server determines a space coordinate converting relation according to marked points of the 3D object and the 3D coordinates.

Abstract: An inductor structure with height limit, which comprises: a conductor formed in a bent shape, and is set with a plurality of bending-portions, wherein a first connecting-pin and a second connecting-pin are respectively set at two ends of the conductor; a first magnetic core set with a first combining-surface, wherein the first combining-surface forms a concave groove to accommodate the conductor; and a second magnetic core set with a second combining-surface, wherein the second combining-surface forms a second concave groove to accommodate the conductor; wherein the second combining-surface is combined on the first combining-surface; wherein the conductor is sheathed and set between the first magnetic core and the second magnetic core, and is set with the first connecting-pin and the second connecting-pin exposedly. Therefore, the present invention can increase the magnetic (coupling) route length under the height limit to produce an effect of increasing the inductance value and current.

Abstract: A space coordinate converting server and method thereof are provided. The space coordinate converting server receives a field video recorded with a 3D object from an image capturing device, and generates a point cloud model accordingly. The space coordinate converting server determines key frames of the field video, and maps the point cloud model to key images of the key frames based on rotation and translation information of the image capturing device for generating a characterized 3D coordinate set. The space coordinate converting server determines 2D coordinates of the 3D object in key images, and selects 3D coordinates from the characterized 3D coordinate set according to the 2D coordinates. The space coordinate converting server determines a space coordinate converting relation according to marked points of the 3D object and the 3D coordinates.

Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.

Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.

Abstract: A memory testing method is provided, by using the computation capability of a controller to receive the testing command the program code of a testing PC to generate random data or use an algorithm to generate testing data of specific format. Then, the method writes the data directly to the flash memory and read the data from the memory again to compare with the original data. The comparison result is transmitted back to the testing PC. The method greatly reduces the memory access frequency and I/O load of the testing PC so as to improve the testing efficiency.

Abstract: A control mechanism for multi-functional chips is provided. By receiving operation signals from the predefined pins of the different operation functions, the present invention accesses the corresponding storage area in the memory module according to the operation signals without using different memory modules and memory controllers corresponding to different operation functions so as to save power and reduce the hardware size. For example, the MegaSIM™ multi-functional chip includes the integration of a plurality of operation functions, such as SD/MMC and ISO 7816. Each operation function uses different communication protocol to provide operation signals through individual to shared predefined pins. For example, MegaSIM™ I/O, Vpp/CLK, GND, CLK RST, and Vcc pins are used by ISO 7816, and Cmd, Data0, and Vpp/CLK pins are used by SD/MMC.