Patents by Inventor Shih-Kang Fu
Shih-Kang Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12205886Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.Type: GrantFiled: July 26, 2022Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20240006233Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Kang FU, Hsien-Chang WU, Ming-Han LEE, Shau-Lin SHUE
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Publication number: 20230386910Abstract: A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11810816Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.Type: GrantFiled: May 13, 2022Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Kang Fu, Ming-Han Lee
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Patent number: 11742239Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.Type: GrantFiled: October 14, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20230118565Abstract: The present disclosure provides a method that includes depositing a metal layer onto a substrate, subtractive patterning the metal layer into first metal lines, and forming at least one second metal line between two adjacent ones of the first metal lines using a damascene process. The first metal lines have a different metallization structure from the at least one second metal line.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11545389Abstract: A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.Type: GrantFiled: October 28, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20220367346Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20220367244Abstract: A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11450602Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.Type: GrantFiled: April 1, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20220270915Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.Type: ApplicationFiled: May 13, 2022Publication date: August 25, 2022Inventors: Shih-Kang FU, Ming-Han LEE
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Patent number: 11342219Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.Type: GrantFiled: September 25, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Kang Fu, Ming-Han Lee
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Publication number: 20220102191Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Shih-Kang FU, Ming-Han LEE
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Publication number: 20220068701Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.Type: ApplicationFiled: October 14, 2021Publication date: March 3, 2022Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11211256Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.Type: GrantFiled: February 26, 2020Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11152255Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.Type: GrantFiled: December 12, 2019Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20210313262Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11127680Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: GrantFiled: June 23, 2017Date of Patent: September 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20210265172Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.Type: ApplicationFiled: February 26, 2020Publication date: August 26, 2021Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20210193507Abstract: A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.Type: ApplicationFiled: October 28, 2020Publication date: June 24, 2021Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue