Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P.sup.+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P.sup.+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.